A
Principal Software Engineer, Security Solutions
Accepting applicationsArteris · Campbell, CA
Full-Time Senior AIC++RTLSoCSystemVerilog
Posted
2d ago
Category
Design
Experience
Senior
Country
United States
Principal Engineer Security Solutions Engineering
Location: Campell, CA
Arteris connects innovation.
Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.
What You’ll Do as a Principal Engineer of Security Solutions Engineering at Arteris
Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. A Principal Engineer operates as a core member of the Research and Development team, establishing current and future architectures, implementing innovative solutions, and ensures that engineering commitments are credible, visible, and reliably delivered. Reporting to the senior Director of engineering, this technical leader architects and builds innovative solutions, mentors junior engineers, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and aligns with the strategy of the product team.
Key Responsibilities
Technical Strategy & Architecture
Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality.
Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs.
Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
Execution & Delivery
Contribute strategy and implementation of software products, including correctness, runtime performance, memory footprint, and scalability.
Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems.
Drive predictable execution from research through productization in a commercial EDA environment.
Organization & Talent
Foster a culture of technical excellence, peer review, and evidence‑based decision making.
Develop future technical leaders within a mixed research and development engineering organization.
Cross‑Functional Leadership
Communicate complex algorithmic issues clearly to non‑specialist stakeholders.
What You Bring
At least 8 years of experience architecting, developing and delivering complex C++ commercial technical applications.
Demonstrated history of technical leadership involving setting product direction and owning outcomes of complex algorithms (quality, runtime, reliability, user experience and memory consumption).
Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms.
Strong grounding in algorithms and data structures for digital logic analysis and transformation.
Practical understanding of SoC design and verification flows and how EDA tools are used in production environments.
Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs.
Excellent communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers.
Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.
Expert programming and debug skills in modern C++.
Proficiency working in Linux.
Must exhibit a collaborative technical style and be able to work well with cross functional teams.
Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities.
This position is based in Campbell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings.
Bonus Points If You Have
Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.
Familiarity with hardware security analysis or security-oriented verification tools
Understanding of RTL/gate-level simulation and debugging.
Experience in the implementation and verification of SoC designs.
Education Requirements
Bachelor’s degree in Computer Science or Electrical Engineering (MS/PhD preferred).
Estimated Base Salary
195,000 to 210,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Arteris
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com.
With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.
Show more Show less
Location: Campell, CA
Arteris connects innovation.
Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive, to the AI in the cloud, Arteris connects the innovative tech that shapes tomorrow.
What You’ll Do as a Principal Engineer of Security Solutions Engineering at Arteris
Join our innovative team and help shape the future of semiconductor technology, specifically hardware security solutions. A Principal Engineer operates as a core member of the Research and Development team, establishing current and future architectures, implementing innovative solutions, and ensures that engineering commitments are credible, visible, and reliably delivered. Reporting to the senior Director of engineering, this technical leader architects and builds innovative solutions, mentors junior engineers, clearly communicates technical strategy, translates complex concepts for non-technical stakeholders, ensures risks are identified early and aligns with the strategy of the product team.
Key Responsibilities
Technical Strategy & Architecture
Define and own the long‑term technical strategy for core hardware security engines, balancing innovation, scalability, and product quality.
Review and challenge architectural and algorithmic decisions made by senior technical staff (architects, principal engineers) for high‑performance, memory‑efficient, and scalable analysis systems operating on very large designs.
Set technical standards for algorithmic rigor, performance benchmarking, regression testing, and release readiness.
Execution & Delivery
Contribute strategy and implementation of software products, including correctness, runtime performance, memory footprint, and scalability.
Ensure correctness, determinism, and debuggability of complex multi‑threaded and distributed systems.
Drive predictable execution from research through productization in a commercial EDA environment.
Organization & Talent
Foster a culture of technical excellence, peer review, and evidence‑based decision making.
Develop future technical leaders within a mixed research and development engineering organization.
Cross‑Functional Leadership
Communicate complex algorithmic issues clearly to non‑specialist stakeholders.
What You Bring
At least 8 years of experience architecting, developing and delivering complex C++ commercial technical applications.
Demonstrated history of technical leadership involving setting product direction and owning outcomes of complex algorithms (quality, runtime, reliability, user experience and memory consumption).
Hands-on depth in at least one major EDA area (e.g., simulation, synthesis, formal verification, equivalence checking, static analysis), with the ability to evaluate architectural tradeoffs and algorithms.
Strong grounding in algorithms and data structures for digital logic analysis and transformation.
Practical understanding of SoC design and verification flows and how EDA tools are used in production environments.
Track record building performant, scalable systems (runtime/memory, concurrency, distributed execution) that can operate on multi-billion gate designs.
Excellent communication skills with the ability to clearly articulate risks, tradeoffs, and outcomes to senior leadership and customers.
Understanding and experience with hardware description languages (Verilog, SystemVerilog, VHDL) and simulation semantics.
Expert programming and debug skills in modern C++.
Proficiency working in Linux.
Must exhibit a collaborative technical style and be able to work well with cross functional teams.
Ability to operate effectively in a fast-paced, high-accountability environment with competing priorities.
This position is based in Campbell CA, but highly qualified remote candidates located anywhere in the continental USA will be considered. Travel will be required for team and/or customer meetings.
Bonus Points If You Have
Relevant work experience is in the domains of Simulation, Synthesis or Formal Verification or similar products.
Familiarity with hardware security analysis or security-oriented verification tools
Understanding of RTL/gate-level simulation and debugging.
Experience in the implementation and verification of SoC designs.
Education Requirements
Bachelor’s degree in Computer Science or Electrical Engineering (MS/PhD preferred).
Estimated Base Salary
195,000 to 210,000 annually. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
About Arteris
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster. Learn more at arteris.com.
With over 300 team members headquartered in Silicon Valley and offices around the world, we work with startups and global tech leaders alike to build the next generation of electronic products. We believe in people, purpose and impact. Join us and help shape what comes next.
Show more Show less