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Principal RTL Design Engineer
Accepting applicationsNXP acquires Kinara, Inc. · Hyderabad, Telangana, India
Full-Time Mid_senior AIASICDFTRTLSOC
Estimated market salary
₹15-27 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Company Description NXP Semiconductors, a global leader in secure connectivity solutions for embedded applications, has acquired Kinara Inc., expanding its capabilities in advanced semiconductor and edge processing technologies. This acquisition strengthens NXP’s portfolio in high-performance, low-power silicon and accelerates innovation for automotive, industrial, and IoT markets. Team members benefit from working in a dynamic, fast-growing environment backed by a well-established global organization with strong technical leadership. Candidates can explore NXP’s latest initiatives, products, and culture through the NXP Semiconductors LinkedIn page to gain insight into ongoing projects and opportunities
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Role Description
Job Location : Hyderabad bangalore Pune Nodia
Experience Level :10 to 20 Years
Role : Principal Digital Design Engineer & Architecture Roles
We are seeking an experienced RTL Designer with strong expertise in micro-architecture development, RTL design, integration, and implementation of complex digital blocks/subsystems. The ideal candidate will have a proven track record of translating architectural specifications into high-quality RTL, driving designs from concept through synthesis and silicon bring-up, and collaborating closely with architecture, verification, DFT, physical design, firmware, and system teams.
The role requires deep knowledge of System Verilog/Verilog RTL design, digital design fundamentals, clock/reset architectures, low-power design techniques, and performance-driven implementation. The candidate should be capable of owning IP/block-level development, resolving functional and timing issues, supporting verification and implementation activities, and ensuring delivery of robust, power-efficient, and high-performance designs for next-generation AI inference accelerators.
Key Responsibilities
Define and implement hardware architectures optimized for AI inference SOC's
Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's
Own features end-to-end: specification → RTL → integration → synthesis → debug
Collaborate with physical design teams on synthesis, timing closure, and power optimization.
Collaborate with verification team to ensure design correctness.
Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.
Required Qualifications
12+ years of experience in ASIC/SoC RTL design
Strong Verilog/SystemVerilog coding skills
Solid understanding of synthesis, timing, and power analysis
Experience with Lint/CDC/RDC flows
Strong debugging and root-cause analysis capability
Contact srinivas.kota@kinara.ai
Show more Show less
.
Role Description
Job Location : Hyderabad bangalore Pune Nodia
Experience Level :10 to 20 Years
Role : Principal Digital Design Engineer & Architecture Roles
We are seeking an experienced RTL Designer with strong expertise in micro-architecture development, RTL design, integration, and implementation of complex digital blocks/subsystems. The ideal candidate will have a proven track record of translating architectural specifications into high-quality RTL, driving designs from concept through synthesis and silicon bring-up, and collaborating closely with architecture, verification, DFT, physical design, firmware, and system teams.
The role requires deep knowledge of System Verilog/Verilog RTL design, digital design fundamentals, clock/reset architectures, low-power design techniques, and performance-driven implementation. The candidate should be capable of owning IP/block-level development, resolving functional and timing issues, supporting verification and implementation activities, and ensuring delivery of robust, power-efficient, and high-performance designs for next-generation AI inference accelerators.
Key Responsibilities
Define and implement hardware architectures optimized for AI inference SOC's
Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's
Own features end-to-end: specification → RTL → integration → synthesis → debug
Collaborate with physical design teams on synthesis, timing closure, and power optimization.
Collaborate with verification team to ensure design correctness.
Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases.
Required Qualifications
12+ years of experience in ASIC/SoC RTL design
Strong Verilog/SystemVerilog coding skills
Solid understanding of synthesis, timing, and power analysis
Experience with Lint/CDC/RDC flows
Strong debugging and root-cause analysis capability
Contact srinivas.kota@kinara.ai
Show more Show less