MT
Principal Physical Design Implementation Engineer
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior AIASICCadenceCalibreDFT
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
11h ago
Category
Design
Experience
Mid_senior
Country
India
Location: Bengaluru, India
Physical Design Implementation Engineer (Mid to Senior Level)
Location: Bengaluru, India
Experience: 5-16 years
Industry: Semiconductors | AI | Networking | ASIC Design
Role Overview
We are looking for hands-on Physical Design implementation engineers to own block- and partition-level implementation for our high-performance AI-networking SoCs. This is an execution role: you will drive designs from netlist to GDSII, run the place-and-route flow day to day, and close timing, power, congestion, and physical-verification goals on advanced FinFET nodes.
Key Responsibilities
Block / Partition Implementation: Own physical implementation of complex blocks and partitions from synthesized netlist through floorplanning, placement, CTS, routing, and final GDSII.
Floorplanning & Power Planning: Build floorplans, macro placement, pin assignments, and power-grid (PG) structures that meet area, timing, congestion, and IR-drop targets.
Timing Closure: Run and close multi-mode, multi-corner (MMMC) timing with the STA team, including setup/hold, SI, and high-fanout net optimization.
Congestion & Routability: Analyze and resolve placement/routing congestion, DRC, and antenna issues to achieve clean physical verification.
PPA Optimization: Iterate hands-on on power, performance, and area trade-offs to deliver best-in-class QoR at the block and partition level.
ECO Implementation: Implement functional and timing ECOs (pre- and post-mask) with minimal disruption to a converged database.
Sign-off: Drive blocks through STA, EM/IR, and physical-verification sign-off and tape-out criteria.
Day-to-Day Flow Execution: Run the P&R flow, debug tool issues, and turn around iterations quickly to hit milestones.
Key Skills
Place & Route Tools: Strong hands-on expertise with Synopsys Fusion Compiler/ICC2 and/or Cadence Innovus.
PD Fundamentals: Deep, practical understanding of floorplanning, placement, CTS, routing, and physical verification.
Timing & Constraints: Solid grasp of STA concepts, SDC constraints, and timing-driven implementation.
Sign-off Awareness: Working knowledge of PrimeTime, Calibre/ICV physical verification, and RedHawk/Voltus power analysis.
Scripting: Proficiency in TCL is essential; strong Python and/or Perl for automation is highly valued.
Process Technology: Hands-on experience on advanced FinFET nodes (7nm/5nm and below).
Problem-Solving: Excellent debugging skills with the ability to independently drive complex blocks to closure.
Communication: Good collaboration skills for day-to-day work with RTL, STA, and DFT engineers.
Preferred Qualifications
Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or a related field.
Experience implementing high-speed networking IPs, SerDes-adjacent logic, or large AI/accelerator partitions.
Familiarity with hierarchical and multi-die / chiplet implementation flows.
Track record of taking real blocks from netlist to clean GDSII.
Show more Show less
Physical Design Implementation Engineer (Mid to Senior Level)
Location: Bengaluru, India
Experience: 5-16 years
Industry: Semiconductors | AI | Networking | ASIC Design
Role Overview
We are looking for hands-on Physical Design implementation engineers to own block- and partition-level implementation for our high-performance AI-networking SoCs. This is an execution role: you will drive designs from netlist to GDSII, run the place-and-route flow day to day, and close timing, power, congestion, and physical-verification goals on advanced FinFET nodes.
Key Responsibilities
Block / Partition Implementation: Own physical implementation of complex blocks and partitions from synthesized netlist through floorplanning, placement, CTS, routing, and final GDSII.
Floorplanning & Power Planning: Build floorplans, macro placement, pin assignments, and power-grid (PG) structures that meet area, timing, congestion, and IR-drop targets.
Timing Closure: Run and close multi-mode, multi-corner (MMMC) timing with the STA team, including setup/hold, SI, and high-fanout net optimization.
Congestion & Routability: Analyze and resolve placement/routing congestion, DRC, and antenna issues to achieve clean physical verification.
PPA Optimization: Iterate hands-on on power, performance, and area trade-offs to deliver best-in-class QoR at the block and partition level.
ECO Implementation: Implement functional and timing ECOs (pre- and post-mask) with minimal disruption to a converged database.
Sign-off: Drive blocks through STA, EM/IR, and physical-verification sign-off and tape-out criteria.
Day-to-Day Flow Execution: Run the P&R flow, debug tool issues, and turn around iterations quickly to hit milestones.
Key Skills
Place & Route Tools: Strong hands-on expertise with Synopsys Fusion Compiler/ICC2 and/or Cadence Innovus.
PD Fundamentals: Deep, practical understanding of floorplanning, placement, CTS, routing, and physical verification.
Timing & Constraints: Solid grasp of STA concepts, SDC constraints, and timing-driven implementation.
Sign-off Awareness: Working knowledge of PrimeTime, Calibre/ICV physical verification, and RedHawk/Voltus power analysis.
Scripting: Proficiency in TCL is essential; strong Python and/or Perl for automation is highly valued.
Process Technology: Hands-on experience on advanced FinFET nodes (7nm/5nm and below).
Problem-Solving: Excellent debugging skills with the ability to independently drive complex blocks to closure.
Communication: Good collaboration skills for day-to-day work with RTL, STA, and DFT engineers.
Preferred Qualifications
Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or a related field.
Experience implementing high-speed networking IPs, SerDes-adjacent logic, or large AI/accelerator partitions.
Familiarity with hierarchical and multi-die / chiplet implementation flows.
Track record of taking real blocks from netlist to clean GDSII.
Show more Show less