AS
Principal Physical Design Engineer (Full Chip Expert)
Accepting applicationsAion Silicon · Hyderabad, Telangana, India
Full-Time Principal ASICCadenceCalibreDFTGenus
Estimated market salary
₹14-25 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
4d ago
Category
Design
Experience
Principal
Country
India
Principal Physical Design Engineer (Full Chip Expert)
Location: Global / Hybrid
Department: Engineering
Reports to: Physical Design Function Lead
Join Aion Silicon and Shape the Future of Semiconductor Innovation
At Aion Silicon, we're seeking an experienced Principal Physical Design Engineer to lead the physical implementation of complex, cutting-edge SoCs and ASICs. This is a senior technical leadership role for a recognised Full-Chip Physical Design expert who thrives on solving complex challenges, mentoring engineering teams, and driving successful tape-outs on advanced technology nodes.
You will take ownership of the complete physical design flow, from RTL/netlist handoff through to final sign-off and GDSII generation, working closely with cross-functional teams across the globe.
What You'll Be Doing
As a Principal Physical Design Engineer, you will:
Lead full-chip physical implementation for complex SoC and ASIC designs.
Define and drive chip-level physical design strategies, methodologies and best practices.
Coordinate closely with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve successful design closure.
Mentor and coach Physical Design engineers, supporting capability development across the team.
Review and approve block-level physical design deliverables before integration.
Lead technical reviews, debug sessions and closure activities.
Support recruitment activities and contribute to building a world-class Physical Design team.
Represent Aion Silicon at universities, conferences and industry events, sharing technical expertise and promoting innovation.
Ensure the team remains at the forefront of industry methodologies, tools and advanced-node technologies.
What We're Looking ForEssential Experience
10+ years of Physical Design experience with a proven track record of full-chip delivery.
Strong expertise in advanced technology nodes, including 7nm, 5nm and below.
Experience delivering multiple complex SoC or ASIC tape-outs.
Demonstrated leadership experience mentoring and developing engineers.
Strong customer engagement and stakeholder management skills.
Excellent communication skills with the ability to influence technical direction across multiple teams.
Technical Expertise
You will bring deep expertise in:
Full-Chip Floorplanning & Integration
Chip-level floorplanning and macro placement
IO ring integration
Hierarchical and flat implementation flows
Pin placement, channel planning and congestion management
Power Planning & Package Integration
Power grid design and optimisation
Multi-voltage domains and power gating
IR drop and electromigration analysis
Bump planning and package co-design
Clock Tree Synthesis
Multi-domain and multi-level CTS
Clock mesh, H-tree and fishbone architectures
Skew, latency and jitter optimisation
Low-power clocking techniques
Placement, Routing & Timing Closure
Full-chip placement and routing
Signal integrity, crosstalk and antenna resolution
MCMM timing analysis
STA sign-off and timing ECO implementation
Hierarchical timing budgeting and closure
Physical Verification & Tape-Out
DRC, LVS and ERC sign-off
RC extraction and correlation
Reliability and noise analysis
GDSII/OASIS generation and foundry handoff
EDA Tool Expertise
Strong working knowledge of one or more industry-leading tool flows, including:
Synopsys (ICC2, Fusion Compiler, PrimeTime, StarRC, ICV)
Cadence (Innovus, Tempus, Voltus, Genus)
Mentor Calibre
Desirable Experience
DFT integration and ECO flows
2.5D/3D-IC and chiplet-based architectures
Advanced packaging technologies
Master's or PhD in a relevant engineering discipline
Personal Attributes
We're looking for someone who:
Leads through collaboration, trust and transparency.
Thrives in a fast-paced environment and enjoys solving complex technical challenges.
Demonstrates strong ownership and accountability.
Has a passion for mentoring and developing others.
Is adaptable, resilient and able to navigate changing priorities.
Embodies Aion Silicon's values and contributes positively to our culture.
Why Join Aion Silicon?
At Aion Silicon, you'll work alongside exceptional engineers on some of the industry's most challenging semiconductor projects. You'll have the opportunity to influence technical strategy, mentor future talent, and help shape the next generation of silicon solutions.
If you're a recognised Full-Chip Physical Design expert ready to make a significant impact, we'd love to hear from you.
Apply today and help us design the future.
Show more Show less
Location: Global / Hybrid
Department: Engineering
Reports to: Physical Design Function Lead
Join Aion Silicon and Shape the Future of Semiconductor Innovation
At Aion Silicon, we're seeking an experienced Principal Physical Design Engineer to lead the physical implementation of complex, cutting-edge SoCs and ASICs. This is a senior technical leadership role for a recognised Full-Chip Physical Design expert who thrives on solving complex challenges, mentoring engineering teams, and driving successful tape-outs on advanced technology nodes.
You will take ownership of the complete physical design flow, from RTL/netlist handoff through to final sign-off and GDSII generation, working closely with cross-functional teams across the globe.
What You'll Be Doing
As a Principal Physical Design Engineer, you will:
Lead full-chip physical implementation for complex SoC and ASIC designs.
Define and drive chip-level physical design strategies, methodologies and best practices.
Coordinate closely with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve successful design closure.
Mentor and coach Physical Design engineers, supporting capability development across the team.
Review and approve block-level physical design deliverables before integration.
Lead technical reviews, debug sessions and closure activities.
Support recruitment activities and contribute to building a world-class Physical Design team.
Represent Aion Silicon at universities, conferences and industry events, sharing technical expertise and promoting innovation.
Ensure the team remains at the forefront of industry methodologies, tools and advanced-node technologies.
What We're Looking ForEssential Experience
10+ years of Physical Design experience with a proven track record of full-chip delivery.
Strong expertise in advanced technology nodes, including 7nm, 5nm and below.
Experience delivering multiple complex SoC or ASIC tape-outs.
Demonstrated leadership experience mentoring and developing engineers.
Strong customer engagement and stakeholder management skills.
Excellent communication skills with the ability to influence technical direction across multiple teams.
Technical Expertise
You will bring deep expertise in:
Full-Chip Floorplanning & Integration
Chip-level floorplanning and macro placement
IO ring integration
Hierarchical and flat implementation flows
Pin placement, channel planning and congestion management
Power Planning & Package Integration
Power grid design and optimisation
Multi-voltage domains and power gating
IR drop and electromigration analysis
Bump planning and package co-design
Clock Tree Synthesis
Multi-domain and multi-level CTS
Clock mesh, H-tree and fishbone architectures
Skew, latency and jitter optimisation
Low-power clocking techniques
Placement, Routing & Timing Closure
Full-chip placement and routing
Signal integrity, crosstalk and antenna resolution
MCMM timing analysis
STA sign-off and timing ECO implementation
Hierarchical timing budgeting and closure
Physical Verification & Tape-Out
DRC, LVS and ERC sign-off
RC extraction and correlation
Reliability and noise analysis
GDSII/OASIS generation and foundry handoff
EDA Tool Expertise
Strong working knowledge of one or more industry-leading tool flows, including:
Synopsys (ICC2, Fusion Compiler, PrimeTime, StarRC, ICV)
Cadence (Innovus, Tempus, Voltus, Genus)
Mentor Calibre
Desirable Experience
DFT integration and ECO flows
2.5D/3D-IC and chiplet-based architectures
Advanced packaging technologies
Master's or PhD in a relevant engineering discipline
Personal Attributes
We're looking for someone who:
Leads through collaboration, trust and transparency.
Thrives in a fast-paced environment and enjoys solving complex technical challenges.
Demonstrates strong ownership and accountability.
Has a passion for mentoring and developing others.
Is adaptable, resilient and able to navigate changing priorities.
Embodies Aion Silicon's values and contributes positively to our culture.
Why Join Aion Silicon?
At Aion Silicon, you'll work alongside exceptional engineers on some of the industry's most challenging semiconductor projects. You'll have the opportunity to influence technical strategy, mentor future talent, and help shape the next generation of silicon solutions.
If you're a recognised Full-Chip Physical Design expert ready to make a significant impact, we'd love to hear from you.
Apply today and help us design the future.
Show more Show less