AT
Principal Physical Design Engineer
Accepting applicationsAcceler8 Talent · San Francisco Bay Area
Full-Time Mid_senior AICadenceDFTInnovusRTL
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Acceler8 Talent is partnering with a well-funded, early-stage AI hardware startup building a next-generation inference platform from the ground up. The team is rethinking how AI systems are designed by combining custom silicon with tightly integrated software and systems engineering to deliver dramatically higher performance and efficiency for large-scale AI workloads. You'll join a world-class engineering team with experience from leading semiconductor and AI companies, helping shape the architecture and implementation of cutting-edge accelerator technology from its earliest stages.
About the Role
As a Senior Physical Design Engineer, you'll take ownership of the complete physical implementation of critical blocks within a high-performance AI accelerator SoC. From early floorplanning through final tapeout signoff, you'll work closely with architects, RTL designers, and software engineers to help bring first-generation silicon to life while laying the foundation for future product generations.
What You'll Do
Own the complete physical design flow for one or more major SoC blocks, from floorplanning through final signoff.
Leverage and help develop AI-assisted implementation methodologies to improve design productivity and accelerate tapeout schedules.
Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
Partner closely with architecture, RTL, verification, and software teams to optimize implementation for performance, power, and area.
Collaborate with EDA vendors and foundry partners to resolve implementation challenges and deliver production-ready silicon.
What We're Looking For
8+ years of experience in physical design for complex, high-performance ASICs at advanced process nodes (7nm or below).
Deep expertise across the full implementation flow, including synthesis, place & route, CTS, timing closure, physical verification, and signoff.
Strong hands-on experience with leading implementation tools such as Cadence Innovus, Synopsys Fusion Compiler, or comparable platforms.
Experience with industry-standard signoff tools including PrimeTime, Tempus, or equivalent.
Proven success working cross-functionally with architects, RTL engineers, EDA vendors, and foundries to deliver complex silicon.
Bonus experience with advanced packaging technologies (2.5D/3D, CoWoS), IR/EM analysis, thermal optimization, signal integrity, or DFT-aware implementation.
Compensation & Benefits
Compensation is competitive and will be determined based on experience, technical expertise, and location. In addition to base salary, the package includes meaningful equity participation, comprehensive medical, dental, and vision coverage, a 401(k), and generous paid time off.
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About the Role
As a Senior Physical Design Engineer, you'll take ownership of the complete physical implementation of critical blocks within a high-performance AI accelerator SoC. From early floorplanning through final tapeout signoff, you'll work closely with architects, RTL designers, and software engineers to help bring first-generation silicon to life while laying the foundation for future product generations.
What You'll Do
Own the complete physical design flow for one or more major SoC blocks, from floorplanning through final signoff.
Leverage and help develop AI-assisted implementation methodologies to improve design productivity and accelerate tapeout schedules.
Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
Partner closely with architecture, RTL, verification, and software teams to optimize implementation for performance, power, and area.
Collaborate with EDA vendors and foundry partners to resolve implementation challenges and deliver production-ready silicon.
What We're Looking For
8+ years of experience in physical design for complex, high-performance ASICs at advanced process nodes (7nm or below).
Deep expertise across the full implementation flow, including synthesis, place & route, CTS, timing closure, physical verification, and signoff.
Strong hands-on experience with leading implementation tools such as Cadence Innovus, Synopsys Fusion Compiler, or comparable platforms.
Experience with industry-standard signoff tools including PrimeTime, Tempus, or equivalent.
Proven success working cross-functionally with architects, RTL engineers, EDA vendors, and foundries to deliver complex silicon.
Bonus experience with advanced packaging technologies (2.5D/3D, CoWoS), IR/EM analysis, thermal optimization, signal integrity, or DFT-aware implementation.
Compensation & Benefits
Compensation is competitive and will be determined based on experience, technical expertise, and location. In addition to base salary, the package includes meaningful equity participation, comprehensive medical, dental, and vision coverage, a 401(k), and generous paid time off.
Show more Show less