TT
Principal Lead ASIC Verification
Accepting applicationsTara Technical Solutions (TTS) · San Jose, CA
Full-Time Principal AIASICRTLSerDesSoC
Posted
2d ago
Category
Verification
Experience
Principal
Country
United States
Principal ASIC Verification Lead:
IPs for ASIC products such as custom AI chips. T
This position is responsible for IP and subsystem verification, including processor subsystem among many other IPs.
Requirements:
• Experience in architecting modern verification environment and test benches
• Deep understanding and knowledge of industry standard verification methodologies and tools
• Hands on and In-depth knowledge in UVM, System Verilog, RTL design and verification
• Proven expertise in defining block and sub-system level test plans, creating reusable test benches, and driving verification closure
• Hands on experience in CDC check, formal verification, functional coverage, gate level debug and emulation tools.
• Very strong debugging and problem-solving skills, proven track record of resolving complex issues under schedule pressure.
• Familiar with systems, knowledge of architecture, protocols, and experiences with SerDes bring up
• Experience and knowledge of processor microarchitectures and bus protocols
• Experience in creating and managing automated verification environment would be a plus
Education/Experience:
• Bachelor in Electrical Engineering, Computer Science or related degree and 12+ years of proven experience in SoC/ASIC verification or Master's Degree in Electrical Engineering, Computer Science or related degree and 10+ years of proven experience in SoC/ASIC verification
Show more Show less
IPs for ASIC products such as custom AI chips. T
This position is responsible for IP and subsystem verification, including processor subsystem among many other IPs.
Requirements:
• Experience in architecting modern verification environment and test benches
• Deep understanding and knowledge of industry standard verification methodologies and tools
• Hands on and In-depth knowledge in UVM, System Verilog, RTL design and verification
• Proven expertise in defining block and sub-system level test plans, creating reusable test benches, and driving verification closure
• Hands on experience in CDC check, formal verification, functional coverage, gate level debug and emulation tools.
• Very strong debugging and problem-solving skills, proven track record of resolving complex issues under schedule pressure.
• Familiar with systems, knowledge of architecture, protocols, and experiences with SerDes bring up
• Experience and knowledge of processor microarchitectures and bus protocols
• Experience in creating and managing automated verification environment would be a plus
Education/Experience:
• Bachelor in Electrical Engineering, Computer Science or related degree and 12+ years of proven experience in SoC/ASIC verification or Master's Degree in Electrical Engineering, Computer Science or related degree and 10+ years of proven experience in SoC/ASIC verification
Show more Show less