Principal Engineer RT (DDR PHY ) Engineer

Job Description :
Be part of the Cadence DDR PHY IP development team responsible for -
-Defining microarchitecture of digital blocks to meet specifications, optimized for performance metrics of timing, area and power.
-Lead and also hands on end to end ASIC design including RTL implementation and design processes of Lint/CDC/SDC definition/STA/Synthesis.
-Collaborate with cross functional teams of Architecture, Verification , Physical Design and Mixed Signal teams , ensure alignment of requirements and driving resolution of issues.
-Mentor junior members of the team.

Requirements :
B.E/M.Tech in Electronics Engineering.
8+ years of relevant experience in Digital Design.
Hands on experience in micro-architecting digital blocks and RTL implementation.
Hands on experience in SDC definition, STA , Lint Checks, CDC and understanding of Synthesis Flows.
Prior experience of working on any of the memory subsystem blocks is highly desirable but not a must.
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