TE

Principal Engineer_PDK, Design Enablement & Design Services

Accepting applications

Tata Electronics · Bengaluru, Karnataka, India

Full-Time Mid_senior AICADENCECalibrePythonTCL
Estimated market salary
₹45-81 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
3d ago
Category
Eda
Experience
Mid_senior
Country
India
About The Company

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

Summary

We are seeking a highly skilled EMIR Engineer to drive development, validation and optimization of reliability verification PDK components. The ideal candidate will have a strong background in EMIR tool flows, Reliability verification, semiconductor device physics and relevant EDA tools, with a focus on creating accurate and efficient RV PDK components for design qualification.

Responsibilities

Develop EMIR tool flow and methodology for a variety of analog process nodes using standard EDA tool
Collaborate across PDK technology development team for technical specification definition, drive development, qualification for enabling the EMIR design flows and methodology
Develop scalable infrastructure for highly efficient development and qualification of reliability verification PDK components.
Write the design rules required for EM IR flows compatible with industry standard EDA Tools.
Assist in development to deployment life cycle of RV PDK components for various process nodes.
Being able to develop ESD PERC design flow and methodology catering to PDK and design teams would be an advantage

QUALIFICATION

Education

BS /MS in EC/EE with minimum 5+ years of relevant industry experience in the EMIR flows, reliability verification domain

Experience

Experience with EMIR CAD flow methodology development.
Experience with Totem, Voltus-FiXL tool for running and verifying EMIR flow
Experience with running simulations and simulation result analysis using any standard EDA tool
Good Programming knowledge in TCL, SVRF, Python, Shell, SKILL etc.
Good knowledge in Redhawk SC, CADENCE Voltus tool flow implementation
Knowledge in Calibre ESD PERC design rules, ESD/EOS flows and methodology would be preferred
Knowledge in PDK collateral development and validation would be an advantage

Skills

In depth understanding of Reliability concepts like Electro Migration (EM), IR Drop, Temperature Effects, PVT dependency, and analog sign off flow knowledge.
Expertise in EMIR rule deck development, EM technology file supporting industry standard EDA tools.
Device level knowledge of ESD operational physics, modelling ESD challenges, experience in running topology , p2p and current density checks and fixing them.
Excellent communication skills, able to clearly articulate internal communication along with solutions to customers and requirements to EDA vendors.
A good team player, with ability to navigate self and team in dynamic, challenging, and ambiguous environment.
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