Principal Engineer, PCIe Verification

BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug.
Very good current working experience of UVM and System Verilog based verification methodology is a must.
Working experience on PCIe protocols Gen4/5.
Working experience on PCIe bring-up and debug on Silicon is a plus.
Past working experience on UCIe protocols is a plus.
Proficiency in C/C++/Python programming is a plus.
Good debug and problem solving skill.
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