MT
Principal Engineer – HBM Design for Test (DFT)
Accepting applicationsMicron Technology · Richardson, TX
Full-Time Mid_senior DFTaiateganspi
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
United States
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.
The Principal Engineer – HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining best‑in‑class DFT solutions across HBM core die and base die spanning multiple HBM families.
This role emphasizes DFT architecture, specification ownership, multi-functional alignment, and program support, supported by strong technical expertise to ensure solutions are robust, scalable, and manufacturable. The role includes a close partnership with DFT Verification to ensure feature completeness, coverage, and readiness for tape‑out and silicon bring‑up.
Key Responsibilities:
Own and implement DFT architecture and feature intent for assigned DFT domains across HBM core die and base die
Ensure DFT solutions enable high‑quality, low‑cost, and manufacturable HBM products
Partner with Design Engineering, Product Engineering, Test, and DFT Verification to:
Translate manufacturing and test needs into clear DFT requirements
Ensure spec‑to‑verification coverage alignment for DFT features and test modes
Identify and resolve DFT‑related issues during build execution, tape‑out, and silicon bring‑up
Serve as the DFT point of contact for assigned programs or functional areas
Drive standardization and reuse of DFT features across HBM families.
Participate in DFT governance activities, including design and verification readiness reviews.
Contribute to documentation, knowledge sharing, and training within the DFT organization.
Minimum Qualifications:
Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
8+ years of experience in semiconductor development with exposure to DFT, verification, test strategy, manufacturability, or silicon debug.
Working knowledge of memory architectures (HBM or DRAM preferred)
Experience influencing DFT requirements, specifications, and verification expectations.
Preferred Qualifications:
Strong multi-functional collaboration skills, including work with verification organizations
Clear written and verbal communication skills
Show more Show less
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.
The Principal Engineer – HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining best‑in‑class DFT solutions across HBM core die and base die spanning multiple HBM families.
This role emphasizes DFT architecture, specification ownership, multi-functional alignment, and program support, supported by strong technical expertise to ensure solutions are robust, scalable, and manufacturable. The role includes a close partnership with DFT Verification to ensure feature completeness, coverage, and readiness for tape‑out and silicon bring‑up.
Key Responsibilities:
Own and implement DFT architecture and feature intent for assigned DFT domains across HBM core die and base die
Ensure DFT solutions enable high‑quality, low‑cost, and manufacturable HBM products
Partner with Design Engineering, Product Engineering, Test, and DFT Verification to:
Translate manufacturing and test needs into clear DFT requirements
Ensure spec‑to‑verification coverage alignment for DFT features and test modes
Identify and resolve DFT‑related issues during build execution, tape‑out, and silicon bring‑up
Serve as the DFT point of contact for assigned programs or functional areas
Drive standardization and reuse of DFT features across HBM families.
Participate in DFT governance activities, including design and verification readiness reviews.
Contribute to documentation, knowledge sharing, and training within the DFT organization.
Minimum Qualifications:
Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
8+ years of experience in semiconductor development with exposure to DFT, verification, test strategy, manufacturability, or silicon debug.
Working knowledge of memory architectures (HBM or DRAM preferred)
Experience influencing DFT requirements, specifications, and verification expectations.
Preferred Qualifications:
Strong multi-functional collaboration skills, including work with verification organizations
Clear written and verbal communication skills
Show more Show less