W&
Principal Engineer
Accepting applicationsWenger & Watson · Bengaluru, Karnataka, India
Full-Time Mid_senior ATEATPGCadenceDFTJTAG
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Test
Experience
Mid_senior
Country
India
Hiring: DFT Architect / Principal DFT Engineer
Locations: Bangalore | Hyderabad | Ahmedabad
Experience: 7+ years
We are looking for experienced DFT Architects / Principal DFT Engineers to drive DFT architecture, methodology, and implementation for next-generation high-performance SoCs and IPs.
Key Responsibilities
Define end-to-end DFT architecture and test strategy for complex SoCs
Lead Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500 implementations
Drive hierarchical DFT integration, test-mode clocking and power-aware test methodologies
Optimize test time, test data volume and manufacturing cost
Collaborate with RTL, Architecture, Physical Design and Product/Test Engineering teams
Lead DFT verification, post-silicon bring-up, ATE validation and failure analysis
Evaluate and establish DFT flows using leading EDA tools
Must-Have Skills
10–15+ years of hands-on DFT design, architecture and verification
Strong expertise in ATPG and advanced fault models
Experience with MBIST/BISR and LBIST
Expertise in hierarchical DFT and core-wrapper methodologies
Proficiency with Synopsys TestMax/TetraMAX, Siemens Tessent or Cadence Modus
Strong understanding of STA and DFT timing closure
Strong scripting skills in Tcl / Perl / Python / Shell
Show more Show less
Locations: Bangalore | Hyderabad | Ahmedabad
Experience: 7+ years
We are looking for experienced DFT Architects / Principal DFT Engineers to drive DFT architecture, methodology, and implementation for next-generation high-performance SoCs and IPs.
Key Responsibilities
Define end-to-end DFT architecture and test strategy for complex SoCs
Lead Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500 implementations
Drive hierarchical DFT integration, test-mode clocking and power-aware test methodologies
Optimize test time, test data volume and manufacturing cost
Collaborate with RTL, Architecture, Physical Design and Product/Test Engineering teams
Lead DFT verification, post-silicon bring-up, ATE validation and failure analysis
Evaluate and establish DFT flows using leading EDA tools
Must-Have Skills
10–15+ years of hands-on DFT design, architecture and verification
Strong expertise in ATPG and advanced fault models
Experience with MBIST/BISR and LBIST
Expertise in hierarchical DFT and core-wrapper methodologies
Proficiency with Synopsys TestMax/TetraMAX, Siemens Tessent or Cadence Modus
Strong understanding of STA and DFT timing closure
Strong scripting skills in Tcl / Perl / Python / Shell
Show more Show less