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Principal Engineer, ASIC Development Engineering (SOC Verification, System Verilog, Flows, Python, Scripting) with 8 to 12 years of experience

Accepting applications

Sandisk · Bengaluru, Karnataka, India

Full-Time Mid_senior ASICPerlPythonSOCSystemVerilog
Estimated market salary
₹27-49 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
15 Jun
Category
Verification
Experience
Mid_senior
Country
India
Company Description

Sandiskunderstands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies,our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandiskmeets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibilityforward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolioof products that are recognized globallyforinnovation, performance and quality.

Sandiskhas two facilities recognized by the World EconomicForum as part of the Global Lighthouse Networkforadvanced 4IR innovations. These facilities were also recognized as Sustainability Lighthousesforbreakthroughs in efficient operations. With ourglobal reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world movingforward.

Job Description

Providing technical leadership and expertise to define requirements for framework through programming/scripting of verification and emulation flows.
Partnering with ASIC engineers to deploy and support framework for technologies like advanced verification environment configuration and management.
Collaborating cross-functionally to optimize verification and emulation workflows and standardize methodologies.

Qualifications

BE or MS degree in Electrical Engineering or Computer Engineering, with 8+ years of experience.
Understanding C, SystemVerilog UVM, coverage driven verification methodology especially testplan creation and constructs of testbench architecture.
Scripting and regression suite development experience using Python, TCL and Perl
Excellentdebugging and problem-solving skillswith simulation and emulation environments.

Skills Required

Proficiency withSystemVerilog UVM and advanced verification methodologies.
GoodProgramming/Scriptingskills with languages such as Python, Perl, TCL and BASH
Working knowledge of Linux/Unix environment and shell scripting
Excellentdebugging and problem-solving skillswith simulation and emulation environments. Experience with test plan creation and execution.
Cross-Functional Collaboration: Ability to work closely withdesign, validation, firmware, and physical design teamsto resolve system-level issues.
Strongteam player, able to collaborate effectively across architecture, design, and validation teams.
Great written and verbal communication skills
Strong team player who can collaborate with colleagues

Additional Information

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us atjobs.accommodations@sandisk.comto advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
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