PI
Principal DSP / SerDes Architect
Accepting applicationsPER International · San Jose, CA
Full-Time Mid_senior C++MatlabPythonRTLSerDes
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
United States
Location: San Jose, CA or Irvine, CA (4 days onsite)
We are partnering with a leading semiconductor company to hire a Principal DSP / SerDes Architect to join a high-impact engineering team working on next-generation high-speed connectivity solutions.
This is a hands-on technical leadership role focused on advanced DSP algorithm development, system architecture, and modeling for high-speed electrical and optical SerDes.
The Role
You will play a key role in defining and developing DSP algorithms and architectures for complex high-speed communication systems. This position requires deep technical expertise, strong ownership, and the ability to operate at a senior staff / principal level while remaining hands-on.
Key responsibilities include:
Develop advanced DSP algorithms and system architectures for high-speed electrical and/or optical SerDes
Build and evaluate system models using Matlab, Python, or C++
Drive architectural trade-offs and optimization across performance, power, and area (PPA)
Support bit-true and cycle-true modeling, design verification, and post-silicon validation
Collaborate closely with analog, digital, and system teams across global locations
Lead or drive key technical initiatives from concept through to silicon
Provide technical leadership and guidance within the DSP / architecture domain
Influence system-level design decisions and overall technical direction
Requirements
MS or PhD in Electrical Engineering, Computer Engineering, or related field
15+ years of experience in DSP, communication systems, or related domains
Deep expertise in digital signal processing and communication theory
Strong experience in high-speed wireline and/or optical communication systems (SerDes)
Proficiency in system modeling using Matlab, Python, or C++
Proven track record of developing algorithms and architectures in production environments
Experience working across modeling, verification, and post-silicon phases
Ability to operate as both a technical authority and hands-on contributor
Preferred Experience
Experience with equalization, CDR-related DSP, compensation/cancellation, sequence detection, or error coding (FEC)
Exposure to both electrical and optical SerDes systems
Understanding of analog circuit design or RTL implementation
Experience collaborating across cross-functional hardware and system teams
Prior experience in leading or mentoring engineers within a technical domain
Additional Information
This is a hands-on role at Principal / Senior Principal level (or above)
Candidates must be willing to work onsite 4 days per week
Relocation support is available for the right candidate
Why Apply?
This is an opportunity to work on advanced high-speed communication systems within a strong engineering environment, with real ownership and impact on next-generation silicon.
If you are operating at a senior level in DSP, SerDes, or communication systems and want to work at the forefront of high-speed architecture and algorithm development, this is a high-impact role to consider.
Show more Show less
We are partnering with a leading semiconductor company to hire a Principal DSP / SerDes Architect to join a high-impact engineering team working on next-generation high-speed connectivity solutions.
This is a hands-on technical leadership role focused on advanced DSP algorithm development, system architecture, and modeling for high-speed electrical and optical SerDes.
The Role
You will play a key role in defining and developing DSP algorithms and architectures for complex high-speed communication systems. This position requires deep technical expertise, strong ownership, and the ability to operate at a senior staff / principal level while remaining hands-on.
Key responsibilities include:
Develop advanced DSP algorithms and system architectures for high-speed electrical and/or optical SerDes
Build and evaluate system models using Matlab, Python, or C++
Drive architectural trade-offs and optimization across performance, power, and area (PPA)
Support bit-true and cycle-true modeling, design verification, and post-silicon validation
Collaborate closely with analog, digital, and system teams across global locations
Lead or drive key technical initiatives from concept through to silicon
Provide technical leadership and guidance within the DSP / architecture domain
Influence system-level design decisions and overall technical direction
Requirements
MS or PhD in Electrical Engineering, Computer Engineering, or related field
15+ years of experience in DSP, communication systems, or related domains
Deep expertise in digital signal processing and communication theory
Strong experience in high-speed wireline and/or optical communication systems (SerDes)
Proficiency in system modeling using Matlab, Python, or C++
Proven track record of developing algorithms and architectures in production environments
Experience working across modeling, verification, and post-silicon phases
Ability to operate as both a technical authority and hands-on contributor
Preferred Experience
Experience with equalization, CDR-related DSP, compensation/cancellation, sequence detection, or error coding (FEC)
Exposure to both electrical and optical SerDes systems
Understanding of analog circuit design or RTL implementation
Experience collaborating across cross-functional hardware and system teams
Prior experience in leading or mentoring engineers within a technical domain
Additional Information
This is a hands-on role at Principal / Senior Principal level (or above)
Candidates must be willing to work onsite 4 days per week
Relocation support is available for the right candidate
Why Apply?
This is an opportunity to work on advanced high-speed communication systems within a strong engineering environment, with real ownership and impact on next-generation silicon.
If you are operating at a senior level in DSP, SerDes, or communication systems and want to work at the forefront of high-speed architecture and algorithm development, this is a high-impact role to consider.
Show more Show less