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Principal DFT Engineer
Accepting applicationsWenger & Watson · Bengaluru, Karnataka, India
Full-Time Mid_senior ScanATPGMBISTJTAGDFT
Estimated market salary
₹44-79 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Test
Experience
Mid_senior
Country
India
DFT Architect / Principal DFT Engineer
Location: Bangalore / Ahmedabad/Hyderabad
Job Description:
As a DFT Architect, you will be responsible for defining the comprehensive test strategy, methodology, and architecture for our next-generation, high-performance SoCs and IPs. You will bridge the gap between architectural concepts, RTL design, physical implementation, and post-silicon manufacturing. The ideal candidate will have deep technical expertise in cutting-edge DFT techniques, a proven track record of delivering complex silicon to production, and the ability to influence cross-functional engineering teams.
Key Responsibilities
● Architecture & Strategy: Define and document the end-to-end DFT architecture for large-scale, advanced-node SoCs, including partitioning, test-mode clocking schemes, and power-aware test methodologies.
● Methodology Development: Establish state-of-the-art DFT methodologies across Scan/ATPG, Memory BIST (MBIST), Logic BIST (LBIST), and Analog/Mixed-Signal test structures.
● Standards Enforcement: Lead the implementation of industry-standard test protocols, including IEEE 1149.1 (JTAG), IEEE 1500, and IEEE 1687 (IJTAG) network architectures.
● Cost & Efficiency Optimization: Drive strategies to optimize Test Time (TAT) and Test Data Volume (TDV) using high-speed interfaces (e.g., PCIe/USB pin-muxing for test) or advanced compression techniques to lower manufacturing costs.
● Cross-Functional Collaboration: Partner closely with Frontend Design, Architecture, Physical Design (STA/Synthesis), and Product/Test Engineering (PTE) teams to ensure DFT compliance and timely closing of timing constraints in test modes.
● Tool Evaluation: Evaluate, deploy, and benchmark industry-leading EDA tools (Synopsys, Siemens/Mentor, Cadence) to establish robust automated DFT insertion and verification flows.
● Post-Silicon Support: Lead post-silicon bring-up, ATE pattern validation, and failure analysis/debug to maximize production yield and meet DPPM goals.
Required Technical Skills & Qualifications
● Education: Bachelor’s / Master’s / Ph.D. degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
● Experience: 10 to 15+ years of core hands-on experience in DFT design, architecture, and verification for complex SoCs.
● ATPG Expertise: Deep understanding of ATPG, pattern generation, and advanced fault models (Stuck-at, Transition, Path Delay, Cell-Aware, and Gate-Exhaustive testing).
● BIST Solutions: Extensive experience with MBIST insertion, memory self-repair (BISR) architectures, and Logic BIST (LBIST) execution.
● Hierarchical Flows: Proven track record with hierarchical DFT structures, core-wrapper approaches, and top-level integration.
● EDA Tools: High proficiency with industry tools such as Siemens Tessent (MaxTest, FastScan, MBIST), Synopsys TestMax (DFTMAX, TetraMAX), or Cadence Modus.
● Timing & Constraints: Strong baseline in Static Timing Analysis (STA) concepts, specifically managing and closing timing for DFT/Scan shift and capture modes.
● Scripting: Expert automation skills using Tcl, Perl, Python, or Shell scripting.
Preferred / Bonus Qualifications
● Experience with Automotive Safety Standards (ISO 26262), including FuSa mechanisms, FMEDA, and In-System Test (IST) diagnostics.
● Experience architecting DFT for advanced packaging technologies, such as 2.5D/3D ICs, Chiplets, or HBM interfaces (IEEE 1838).
● Strong understanding of ATE tester architectures and direct experience debugging patterns on silicon/hardware testers.
Soft Skills
● Strong leadership qualities with the ability to mentor junior and mid-level DFT execution engineers.
● Excellent technical documentation and presentation skills to justify architectural tradeoffs to engineering executives.
● Problem-solving mindset with an capability to thrive under tight production deadlines.
Show more Show less
Location: Bangalore / Ahmedabad/Hyderabad
Job Description:
As a DFT Architect, you will be responsible for defining the comprehensive test strategy, methodology, and architecture for our next-generation, high-performance SoCs and IPs. You will bridge the gap between architectural concepts, RTL design, physical implementation, and post-silicon manufacturing. The ideal candidate will have deep technical expertise in cutting-edge DFT techniques, a proven track record of delivering complex silicon to production, and the ability to influence cross-functional engineering teams.
Key Responsibilities
● Architecture & Strategy: Define and document the end-to-end DFT architecture for large-scale, advanced-node SoCs, including partitioning, test-mode clocking schemes, and power-aware test methodologies.
● Methodology Development: Establish state-of-the-art DFT methodologies across Scan/ATPG, Memory BIST (MBIST), Logic BIST (LBIST), and Analog/Mixed-Signal test structures.
● Standards Enforcement: Lead the implementation of industry-standard test protocols, including IEEE 1149.1 (JTAG), IEEE 1500, and IEEE 1687 (IJTAG) network architectures.
● Cost & Efficiency Optimization: Drive strategies to optimize Test Time (TAT) and Test Data Volume (TDV) using high-speed interfaces (e.g., PCIe/USB pin-muxing for test) or advanced compression techniques to lower manufacturing costs.
● Cross-Functional Collaboration: Partner closely with Frontend Design, Architecture, Physical Design (STA/Synthesis), and Product/Test Engineering (PTE) teams to ensure DFT compliance and timely closing of timing constraints in test modes.
● Tool Evaluation: Evaluate, deploy, and benchmark industry-leading EDA tools (Synopsys, Siemens/Mentor, Cadence) to establish robust automated DFT insertion and verification flows.
● Post-Silicon Support: Lead post-silicon bring-up, ATE pattern validation, and failure analysis/debug to maximize production yield and meet DPPM goals.
Required Technical Skills & Qualifications
● Education: Bachelor’s / Master’s / Ph.D. degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
● Experience: 10 to 15+ years of core hands-on experience in DFT design, architecture, and verification for complex SoCs.
● ATPG Expertise: Deep understanding of ATPG, pattern generation, and advanced fault models (Stuck-at, Transition, Path Delay, Cell-Aware, and Gate-Exhaustive testing).
● BIST Solutions: Extensive experience with MBIST insertion, memory self-repair (BISR) architectures, and Logic BIST (LBIST) execution.
● Hierarchical Flows: Proven track record with hierarchical DFT structures, core-wrapper approaches, and top-level integration.
● EDA Tools: High proficiency with industry tools such as Siemens Tessent (MaxTest, FastScan, MBIST), Synopsys TestMax (DFTMAX, TetraMAX), or Cadence Modus.
● Timing & Constraints: Strong baseline in Static Timing Analysis (STA) concepts, specifically managing and closing timing for DFT/Scan shift and capture modes.
● Scripting: Expert automation skills using Tcl, Perl, Python, or Shell scripting.
Preferred / Bonus Qualifications
● Experience with Automotive Safety Standards (ISO 26262), including FuSa mechanisms, FMEDA, and In-System Test (IST) diagnostics.
● Experience architecting DFT for advanced packaging technologies, such as 2.5D/3D ICs, Chiplets, or HBM interfaces (IEEE 1838).
● Strong understanding of ATE tester architectures and direct experience debugging patterns on silicon/hardware testers.
Soft Skills
● Strong leadership qualities with the ability to mentor junior and mid-level DFT execution engineers.
● Excellent technical documentation and presentation skills to justify architectural tradeoffs to engineering executives.
● Problem-solving mindset with an capability to thrive under tight production deadlines.
Show more Show less