F

Principal DFT Engineer

Accepting applications

Fortell · San Francisco Bay Area

Full-Time Mid_senior AIATPGBISTCadenceDFT
Posted
22 Apr
Category
Test
Experience
Mid_senior
Country
United States
Fortell is building breakthrough AI-powered hearing technology that redefines how people experience sound and connect with the world. Powered by custom silicon and advances in hearing science, our hearing aids help people hear, and live, with greater clarity and confidence.


We’re looking for an experienced DFT Engineer to lead full-chip test architecture, from scan and compression logic to MBIST and silicon debug. You’ll collaborate across STA, physical design, memory, and test teams to deliver production-ready silicon with world-class test coverage and diagnostic capability

Job Responsibilities
Develop, architect and implement comprehensive DFT structures tailored to specific design requirements, including full-scan, boundary scan, and memory test strategies
Design and implement robust DFT infrastructure, including scan chains, compression logic, MBIST, BIST, JTAG, and other test mechanism
Generate high-quality ATPG test vectors for logic and memory, and analyze DFT coverage to ensure thorough fault detection and diagnostic capabilities
Perform MBIST verification including simulation of memory test algorithms, fault modeling, and debug of failing pattern
Verify test patterns using gate-level simulations to identify and address functional or timing-related issue
Collaborate closely with STA, physical design, power, and memory compiler teams to debug and resolve DFT/MBIST-related challenge
Work in partnership with test engineers to bring up scan and MBIST vectors on silicon, support silicon debug, and ensure successful production testing

Preferred Qualifications
Strong understanding of industry standards and best practices in DFT, ATPG, JTAG, and MBI
Proven experience in developing DFT specifications and architectures for complex design
Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more
Proficiency in Cadence tools like Modus and Genus for DFT implementation, vector generation, and verification
Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes
Efficient scripting skills using TCL for automating tasks and developing custom flow

Candidates must reside in the Bay Area and be available for occasional in-person collaboration, with plans to establish a local office in the future. Occasional travel to other company locations may be required.
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