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Principal Design Verification Lead
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Principal ASICDDRDFTPCIeRTL
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Principal
Country
India
Principal Design Verification LeadAbout the Role
LeadIC Design Pvt Ltd is looking for a Principal Design Verification Lead with 10+ years of experience in ASIC/SoC Design Verification to lead DV teams and drive verification architecture for complex SoC/IP programs.
This role combines SoC Verification Architecture, Testbench Architecture, and DV Technical Leadership. The ideal candidate should be hands-on technically and experienced in leading engineers, defining verification strategies, architecting scalable UVM environments, and driving projects to verification closure.
Key Responsibilities
Lead and mentor a team of Design Verification engineers.
Define SoC/IP verification strategy, architecture, planning, and sign-off criteria.
Architect scalable and reusable SystemVerilog/UVM testbenches.
Drive constrained-random, coverage-driven, assertion-based verification and coverage closure.
Review testbenches, verification plans, test cases, coverage, and debug results.
Lead complex verification debug and root-cause analysis.
Work closely with RTL, architecture, firmware, DFT, and validation teams.
Drive verification methodology, automation, reuse, quality, and technical best practices.
Required Skills
10+ years of ASIC/SoC Design Verification experience.
Strong hands-on expertise in SystemVerilog and UVM.
Experience in SoC verification architecture and testbench architecture.
Strong knowledge of functional coverage, code coverage, SVA, constrained-random verification, regression, and debug.
Proven experience leading DV teams or complex verification projects.
Strong understanding of RTL, micro-architecture, and SoC verification.
Excellent technical leadership, communication, and mentoring skills.
Preferred
Experience with AMBA (AXI/ACE/CHI), PCIe, DDR, NoC, cache coherency, low-power verification, formal, emulation, or HW/SW co-verification is a plus.
Ideal Candidate
DV Lead | SoC Verification Lead | DV Architect | Verification Architect | Testbench Architect | Principal DV Engineer | Staff DV Engineer
Location: Bengaluru | Workplace: Hybrid | Job Type: Full-time
Interested?
If this opportunity matches your experience in SoC Verification, Testbench Architecture, and DV Technical Leadership, please share your profile at nagu.ms@leadicdesign.com or reach out to me directly on LinkedIn.
Show more Show less
LeadIC Design Pvt Ltd is looking for a Principal Design Verification Lead with 10+ years of experience in ASIC/SoC Design Verification to lead DV teams and drive verification architecture for complex SoC/IP programs.
This role combines SoC Verification Architecture, Testbench Architecture, and DV Technical Leadership. The ideal candidate should be hands-on technically and experienced in leading engineers, defining verification strategies, architecting scalable UVM environments, and driving projects to verification closure.
Key Responsibilities
Lead and mentor a team of Design Verification engineers.
Define SoC/IP verification strategy, architecture, planning, and sign-off criteria.
Architect scalable and reusable SystemVerilog/UVM testbenches.
Drive constrained-random, coverage-driven, assertion-based verification and coverage closure.
Review testbenches, verification plans, test cases, coverage, and debug results.
Lead complex verification debug and root-cause analysis.
Work closely with RTL, architecture, firmware, DFT, and validation teams.
Drive verification methodology, automation, reuse, quality, and technical best practices.
Required Skills
10+ years of ASIC/SoC Design Verification experience.
Strong hands-on expertise in SystemVerilog and UVM.
Experience in SoC verification architecture and testbench architecture.
Strong knowledge of functional coverage, code coverage, SVA, constrained-random verification, regression, and debug.
Proven experience leading DV teams or complex verification projects.
Strong understanding of RTL, micro-architecture, and SoC verification.
Excellent technical leadership, communication, and mentoring skills.
Preferred
Experience with AMBA (AXI/ACE/CHI), PCIe, DDR, NoC, cache coherency, low-power verification, formal, emulation, or HW/SW co-verification is a plus.
Ideal Candidate
DV Lead | SoC Verification Lead | DV Architect | Verification Architect | Testbench Architect | Principal DV Engineer | Staff DV Engineer
Location: Bengaluru | Workplace: Hybrid | Job Type: Full-time
Interested?
If this opportunity matches your experience in SoC Verification, Testbench Architecture, and DV Technical Leadership, please share your profile at nagu.ms@leadicdesign.com or reach out to me directly on LinkedIn.
Show more Show less