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Principal Design Verification Engineer – CXL / PCIe / Ethernet
Accepting applicationsAstera Labs · Bengaluru, Karnataka, India
Full-Time Principal AICadenceDDREthernetFPGA
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Verification
Experience
Principal
Country
India
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Design Verification Engineer – CXL / PCIe / Ethernet
About Astera Labs
Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing by delivering scalable, high-performance solutions based on industry-leading standards such as PCI Express (PCIe), Compute Express Link (CXL), and Ethernet.
Role Overview
We are seeking an experienced Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.
The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.
Key Responsibilities
Technical Leadership
Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
Drive verification planning, execution, coverage closure, and sign-off.
Identify verification risks early and proactively drive mitigation plans.
Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.
Design Verification
Architect and develop scalable UVM/SystemVerilog verification environments.
Develop constrained-random, coverage-driven verification methodologies.
Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.
Debug complex RTL, protocol, timing, and integration issues.
Drive regression planning, automation, and continuous integration improvements.
Develop reusable VIP and verification infrastructure across multiple product lines.
Protocol Verification
Lead Verification Efforts Involving One Or More Of
Compute Express Link (CXL 2.x / 3.x)
PCI Express (Gen4/Gen5/Gen6)
Ethernet (10G–800G)
AXI, APB, AHB
High-speed SerDes interfaces
Memory interfaces including DDR/LPDDR/HBM (preferred)
Cross-Functional Collaboration
Work closely with Architecture teams to influence design for verification.
Partner with RTL designers during implementation and debug.
Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams.
Support customer issue analysis and silicon bring-up when required.
Technical Mentorship
Mentor and coach verification engineers across multiple experience levels.
Establish verification standards and engineering excellence across the organization.
Drive innovation in automation, verification productivity, and quality metrics.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
Strong expertise in SystemVerilog and UVM.
Extensive experience in verification planning, execution, and sign-off.
Deep understanding of constrained-random verification and coverage-driven methodologies.
Strong experience with assertions (SVA), functional coverage, and protocol compliance.
Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.
Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Preferred Technical Expertise
Strong experience in several of the following areas:
CXL Cache, Memory, and I/O protocols
PCIe Transaction, Data Link, and Physical Layers
Ethernet MAC/PCS/PMA architecture
Coherency protocols
High-speed interconnects
AI accelerator connectivity
Data center SoC architecture
Multi-chip and chiplet-based systems
Performance verification
Low-power verification
CDC/RDC verification
Formal Verification
Portable Stimulus (PSS)
Python, Perl, Tcl, or similar scripting languages
Emulation and FPGA prototyping
Leadership Expectations
Own technical direction for large verification programs.
Influence architecture and product quality through early engagement.
Drive cross-functional execution across geographically distributed teams.
Establish reusable verification IP and methodology.
Mentor engineers and help grow technical capability within the organization.
Champion engineering excellence, quality, and continuous improvement.
Preferred Experience
Experience leading verification for large SoCs or complex connectivity IPs.
Proven success delivering multiple first-pass silicon programs.
Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.
Familiarity with customer-facing debug and post-silicon issue resolution.
Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus.
Why Astera Labs?
At Astera Labs, you will help shape the future of AI and cloud infrastructure by developing industry-leading connectivity solutions. You'll work with some of the brightest engineers in the industry, solve challenging technical problems at scale, and influence the architecture and verification of products deployed by the world's leading hyperscalers and OEMs. This role offers significant technical ownership, leadership opportunities, and the chance to make a lasting impact on next-generation semiconductor innovation.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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Principal Design Verification Engineer – CXL / PCIe / Ethernet
About Astera Labs
Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing by delivering scalable, high-performance solutions based on industry-leading standards such as PCI Express (PCIe), Compute Express Link (CXL), and Ethernet.
Role Overview
We are seeking an experienced Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.
The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.
Key Responsibilities
Technical Leadership
Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
Drive verification planning, execution, coverage closure, and sign-off.
Identify verification risks early and proactively drive mitigation plans.
Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.
Design Verification
Architect and develop scalable UVM/SystemVerilog verification environments.
Develop constrained-random, coverage-driven verification methodologies.
Design scoreboards, protocol monitors, checkers, assertions (SVA), and functional coverage models.
Debug complex RTL, protocol, timing, and integration issues.
Drive regression planning, automation, and continuous integration improvements.
Develop reusable VIP and verification infrastructure across multiple product lines.
Protocol Verification
Lead Verification Efforts Involving One Or More Of
Compute Express Link (CXL 2.x / 3.x)
PCI Express (Gen4/Gen5/Gen6)
Ethernet (10G–800G)
AXI, APB, AHB
High-speed SerDes interfaces
Memory interfaces including DDR/LPDDR/HBM (preferred)
Cross-Functional Collaboration
Work closely with Architecture teams to influence design for verification.
Partner with RTL designers during implementation and debug.
Collaborate with Firmware, Emulation, FPGA, Post-Silicon Validation, and System Engineering teams.
Support customer issue analysis and silicon bring-up when required.
Technical Mentorship
Mentor and coach verification engineers across multiple experience levels.
Establish verification standards and engineering excellence across the organization.
Drive innovation in automation, verification productivity, and quality metrics.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Minimum10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
Strong expertise in SystemVerilog and UVM.
Extensive experience in verification planning, execution, and sign-off.
Deep understanding of constrained-random verification and coverage-driven methodologies.
Strong experience with assertions (SVA), functional coverage, and protocol compliance.
Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.
Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Preferred Technical Expertise
Strong experience in several of the following areas:
CXL Cache, Memory, and I/O protocols
PCIe Transaction, Data Link, and Physical Layers
Ethernet MAC/PCS/PMA architecture
Coherency protocols
High-speed interconnects
AI accelerator connectivity
Data center SoC architecture
Multi-chip and chiplet-based systems
Performance verification
Low-power verification
CDC/RDC verification
Formal Verification
Portable Stimulus (PSS)
Python, Perl, Tcl, or similar scripting languages
Emulation and FPGA prototyping
Leadership Expectations
Own technical direction for large verification programs.
Influence architecture and product quality through early engagement.
Drive cross-functional execution across geographically distributed teams.
Establish reusable verification IP and methodology.
Mentor engineers and help grow technical capability within the organization.
Champion engineering excellence, quality, and continuous improvement.
Preferred Experience
Experience leading verification for large SoCs or complex connectivity IPs.
Proven success delivering multiple first-pass silicon programs.
Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.
Familiarity with customer-facing debug and post-silicon issue resolution.
Contributions to verification methodology, reusable frameworks, or industry standards are a strong plus.
Why Astera Labs?
At Astera Labs, you will help shape the future of AI and cloud infrastructure by developing industry-leading connectivity solutions. You'll work with some of the brightest engineers in the industry, solve challenging technical problems at scale, and influence the architecture and verification of products deployed by the world's leading hyperscalers and OEMs. This role offers significant technical ownership, leadership opportunities, and the chance to make a lasting impact on next-generation semiconductor innovation.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Show more Show less