Principal Design Verification Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is looking for a Principal Design Verification Engineer with a passion for breaking complex designs and developing innovative verification strategies for next-generation AI connectivity ASICs. You'll leverage your deep expertise in SystemVerilog, UVM, and hybrid verification methodologies to ensure the highest quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

In this role, you'll own the full verification lifecycle—from test planning through coverage closure—while collaborating with RTL designers, software teams, and system validation engineers. You'll drive verification of excellence, mentor team members, and contribute to methodology improvements that scale across multiple product lines in a fast-paced, high-impact environment.

Key Responsibilities

Verification Strategy & Execution
Define and execute comprehensive verification strategies using hybrid directed and constrained-random methodologies with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
Own the full verification lifecycle from test plan development through coverage closure and tape-out sign-off
Develop and deploy advanced coverage models to identify verification holes and ensure high-quality silicon
Technical Problem Solving
Debug complex design issues collaboratively with RTL designers, driving root cause analysis to resolution
Implement formal verification techniques to complement simulation-based approaches
Develop test sequences and stimulus generation for corner-case coverage
Collaboration & Leadership
Partner with software and system validation teams to develop and execute test plans on emulation platforms
Mentor junior verification engineers and drive best practices across the team
Contribute to verification infrastructure improvements and automation initiatives
Basic Qualifications

Bachelor's degree in Electrical Engineering; Master's preferred
10+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
Expert-level proficiency with SystemVerilog/UVM-based verification methodologies
Proven ability to develop and execute test plans, stimulus generation, and coverage closure strategies
Experience with industry-standard simulators, revision control systems, and regression infrastructure
Strong debugging skills with ability to work independently and collaboratively with design teams

Preferred Qualifications

Master's degree in Electrical Engineering or related field
Experience with Verification IPs for protocols such as PCIe (Gen 5+), CXL, Ethernet, DDR4/5, or similar
Proficiency with formal verification methods and tools
Working experience with scripting tools (Python/Perl) to automate verification infrastructure
Experience with emulation platforms and hardware-software co-verification
Background in cache verification or directed test methodologies

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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