AL
Principal ATE High Speed Test Engineer
Accepting applicationsAstera Labs · San Jose, CA
Full-Time Mid_senior ATEBISTC++DDRDFT
Posted
5d ago
Category
Test
Experience
Mid_senior
Country
United States
We are looking for a Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.
Basic Qualification
sStrong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred
.≥8-year experience releasing complex SoC/silicon products to high volume manufacturing
.Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc
.Professional attitude with ability to execute on multiple tasks with minimal supervision
.Strong team player with good communication skills to work alongside a team of high caliber engineers
.Entrepreneurial, open-mind behavior and can-do attitude
.
Required Experien
ceHands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platform
s.Collaboration with design team to define test strategy, create and own test pla
n.Tester platform selection, design, and development of ATE hardware for wafer sort and final tes
t.Familiar with high-speed load board design technique
s.Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product qualit
y.Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional test
s.Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG et
c.Expertise in production test of high speed SerDes operating at 16Gbps and highe
r.Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debu
g.Experience with lab equipment including protocol analyzers and oscilloscope
s.Experience with using Advantest 93k ATE platfor
m.Proficiency in, at least, one modern programming language such as C/C++, Pytho
n.
Preferred Experie
nceFluent in data processing using high level programming languag
es.Experience in running External loopback at wafer so
rt.Familiarity with modern databa
ses
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Basic Qualification
sStrong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred
.≥8-year experience releasing complex SoC/silicon products to high volume manufacturing
.Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc
.Professional attitude with ability to execute on multiple tasks with minimal supervision
.Strong team player with good communication skills to work alongside a team of high caliber engineers
.Entrepreneurial, open-mind behavior and can-do attitude
.
Required Experien
ceHands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platform
s.Collaboration with design team to define test strategy, create and own test pla
n.Tester platform selection, design, and development of ATE hardware for wafer sort and final tes
t.Familiar with high-speed load board design technique
s.Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product qualit
y.Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional test
s.Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG et
c.Expertise in production test of high speed SerDes operating at 16Gbps and highe
r.Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debu
g.Experience with lab equipment including protocol analyzers and oscilloscope
s.Experience with using Advantest 93k ATE platfor
m.Proficiency in, at least, one modern programming language such as C/C++, Pytho
n.
Preferred Experie
nceFluent in data processing using high level programming languag
es.Experience in running External loopback at wafer so
rt.Familiarity with modern databa
ses
Show more Show less