Principal ASIC Engineer

We’re hiring a Senior Principal Digital ASIC Lead to drive next-generation wireless/RF silicon development focused on radar, 5G, and SATCOM platforms.
This is a high-impact leadership role for someone who enjoys owning digital architecture and
execution across complex mixed-signal SoCs — from RTL through silicon validation.

Key areas:
• Wireless/modem/radar SoC architecture
• RTL & micro-architecture (SystemVerilog/Verilog)
• Mixed-signal/RFIC integration
• RISC-V / embedded subsystems
• Silicon bring-up, verification, DFT, timing closure
• Cross-functional leadership across RF, firmware, DV & PD teams

Ideal background:
✔ Wireless ASIC / modem / PHY architecture
✔ 15+ years in Digital ASIC/SoC design
✔ Tapeout & silicon success in advanced nodes
✔ Strong system-level and implementation depth

This is not a generic RTL role — we’re looking for engineers who can influence architecture, execution, and product direction in advanced communication systems.

San Diego-based opportunity. Feel free to message me directly if interested or if you know someone strong in wireless ASIC architecture.
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