BN
PLL Design Architect
Accepting applicationsBest NanoTech · Noida, Uttar Pradesh, India
Full-Time Senior AnalogCMOSCadenceMATLABMentor
Posted
3d ago
Category
Design
Experience
Senior
Country
India
Location: Noida, India
Work Mode: Onsite
Experience: 8 15 Years
1. Role Overview
We are looking for an experienced PLL Design Architect to lead the architecture and design of high-performance Phase-Locked Loop (PLL) systems for advanced semiconductor applications. The role involves defining system-level specifications, driving circuit-level implementation, and ensuring robust silicon performance across process, voltage, and temperature (PVT) conditions. 3. Required Qualifications 4. Technical Skills PLL & Analog Design Circuit Design Expertise Tools & Simulation Process & Silicon
Key Responsibilities
Define and develop PLL architectures including Integer-N, Fractional-N, ADPLL, and LC PLL
Design and optimize critical PLL building blocks such as PFD, Charge Pump, Loop Filter, VCO, and Frequency Dividers
Perform detailed analysis of phase noise, jitter, loop stability, and frequency synthesis performance
Drive architecture trade-offs for power, performance, and area (PPA) optimization
Ensure robust design across PVT corners with parasitic-aware simulations
Perform system-level modeling and verification using MATLAB or equivalent tools
Collaborate with layout teams for analog layout reviews and parasitic extraction considerations
Lead silicon bring-up, debugging, and characterization activities
Analyze silicon results and correlate with pre-silicon simulations
Work closely with digital, mixed-signal, and system teams for integration
Mentor junior engineers and provide technical guidance
Participate in design reviews and documentation of architecture and design decisions
B.Tech / M.Tech / PhD in Electronics, Electrical Engineering, or related field
8+ years of experience in Analog / RF IC design with strong PLL design exposure
Proven track record of successful silicon tape-outs
Strong understanding of PLL system architecture and circuit design
Phase-Locked Loop (PLL) design and architecture
Loop dynamics, stability, phase noise, and jitter analysis
Integer-N, Fractional-N, ADPLL, LC PLL
Phase Frequency Detector (PFD)
Charge Pump design
Voltage Controlled Oscillator (VCO)
Loop Filter design
High-speed frequency dividers
Cadence Virtuoso
Spectre / SpectreRF
MATLAB / System modeling tools
CMOS technology nodes (advanced nodes preferred)
Parasitic extraction and post-layout simulations
Silicon bring-up and validation
Show more Show less
Work Mode: Onsite
Experience: 8 15 Years
1. Role Overview
We are looking for an experienced PLL Design Architect to lead the architecture and design of high-performance Phase-Locked Loop (PLL) systems for advanced semiconductor applications. The role involves defining system-level specifications, driving circuit-level implementation, and ensuring robust silicon performance across process, voltage, and temperature (PVT) conditions. 3. Required Qualifications 4. Technical Skills PLL & Analog Design Circuit Design Expertise Tools & Simulation Process & Silicon
Key Responsibilities
Define and develop PLL architectures including Integer-N, Fractional-N, ADPLL, and LC PLL
Design and optimize critical PLL building blocks such as PFD, Charge Pump, Loop Filter, VCO, and Frequency Dividers
Perform detailed analysis of phase noise, jitter, loop stability, and frequency synthesis performance
Drive architecture trade-offs for power, performance, and area (PPA) optimization
Ensure robust design across PVT corners with parasitic-aware simulations
Perform system-level modeling and verification using MATLAB or equivalent tools
Collaborate with layout teams for analog layout reviews and parasitic extraction considerations
Lead silicon bring-up, debugging, and characterization activities
Analyze silicon results and correlate with pre-silicon simulations
Work closely with digital, mixed-signal, and system teams for integration
Mentor junior engineers and provide technical guidance
Participate in design reviews and documentation of architecture and design decisions
B.Tech / M.Tech / PhD in Electronics, Electrical Engineering, or related field
8+ years of experience in Analog / RF IC design with strong PLL design exposure
Proven track record of successful silicon tape-outs
Strong understanding of PLL system architecture and circuit design
Phase-Locked Loop (PLL) design and architecture
Loop dynamics, stability, phase noise, and jitter analysis
Integer-N, Fractional-N, ADPLL, LC PLL
Phase Frequency Detector (PFD)
Charge Pump design
Voltage Controlled Oscillator (VCO)
Loop Filter design
High-speed frequency dividers
Cadence Virtuoso
Spectre / SpectreRF
MATLAB / System modeling tools
CMOS technology nodes (advanced nodes preferred)
Parasitic extraction and post-layout simulations
Silicon bring-up and validation
Show more Show less