Physical Designer/ ASIC Engineer

Job Title: Physical Designer/ ASIC Engineer
Location: Minneapolis, MN
Duration: 10 Months
Oversees definition, design, verification, and documentation for ASIC development.
Determines architecture design, logic design, and system simulation.
Defines module interfaces/formats for simulation.
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. 7-10 years of experience
We are seeking an experienced contract Physical Design Engineer to own the complete back-end implementation of a high-speed interface test chip — from synthesized netlist through GDSII tape-out. This is a time-bound, high-impact engagement — not a staff augmentation role.
The target vehicle is a 36 I/O full-duplex die-to-die interconnect PHY test chip with integrated characterization functions including internal eye monitoring, internal error counting (PRBS-based), and I2C-based control and management. The PHY is largely custom-designed — this is a technically rich mixed-signal physical design challenge, not a macro-integration exercise. You will work in close collaboration with world-class analog designers, a 30-year layout veteran, and the digital Chip Lead, united around the goal of carrying this test chip to tape-out within the contract window.

What You’ll Own
Floorplanning: Define and implement the full chip floorplan in close collaboration with the analog design team — including custom analog block placement, analog/digital partitioning, I/O ring architecture, power domain definition, and block-level area allocation.
Power Planning: Design and implement the chip power distribution network (PDN); coordinate with the analog team on analog supply isolation, guard ring placement, and substrate noise considerations.
Place & Route: Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and optimized database across all required corners and modes.
Timing Closure: Own static timing analysis (Cadence Tempus) across all PVT corners and modes; identify and resolve timing violations through ECO, placement, and routing optimization; coordinate with the Chip Lead on constraint refinement.
Power Integrity: Perform IR drop and electromigration analysis (Cadence Voltus or equivalent); identify and resolve PDN weaknesses.
Physical Verification Sign-off: Execute and close DRC, LVS, and ERC to foundry-clean status using Mentor Calibre; manage waiver process for any non-cleanable violations.
DFT Integration: Implement scan chain insertion and work with the Chip Lead on ATPG pattern generation and test coverage targets.
Foundry Coordination: Interface with foundry on PDK questions, fill rule implementation, and tape-out submission requirements.
Documentation: Maintain PD methodology documentation, floorplan rationale records, and ECO history to support program continuity and knowledge transfer at contract close. GDSII tape-out sign-off is the primary deliverable of this contract.

What You Bring
RequiredBS, MS, or PhD in Electrical Engineering or related field
8–15 years of physical design experience with at least one complete front-to-back tape-out as the primary or lead PD engineer
Hands-on proficiency with Cadence Innovus for place-and-route — comfortable navigating complex placement constraints, congestion-driven routing, and post-route optimization without step-by-step guidance
Hands-on proficiency with Cadence Tempus for static timing analysis including MMMC setup, OCV/AOCV analysis, and ECO-driven timing closure
Hands-on proficiency with Mentor Calibre for DRC, LVS, and ERC sign-off
Experience placing and integrating hard macros (analog PHY blocks, memory compilers, I/O cells) within a constrained mixed-signal floorplan
Demonstrated ability to take broad ownership and drive to closure — comfortable leading implementation decisions, working across disciplines, and managing priorities without a large supporting PD organization
Strong debugging and root-cause analysis skills — the ability to look at a failing DRC deck, a congested routing region, or a timing path that doesn’t respond to standard approaches and find a path forward
Ability to hit the ground running — this engagement has a fixed end date tied to tape-out; ramp time is minimal by design
Clear communicator across disciplines — able to discuss physical implementation constraints and their design implications with Chip Lead, analog designers, and verification engineers

Preferred
Experience with mixed-signal or analog-adjacent chip physical design — including analog supply domain implementation, substrate isolation techniques, and analog/digital floor separation
Familiarity with high-speed I/O pad ring design for differential full-duplex interfaces
Experience with power domain implementation using UPF/CPF for multi-voltage PHY designs
Proficiency with Cadence Voltus or Apache Redhawk for power integrity analysis
Familiarity with Synopsys IC Compiler 2 (ICC2) as an alternative P&R environment
Experience with signoff ECO flows — functional and metal-only ECOs post-tape-out
Prior contract or startup experience — comfort operating where role boundaries are defined by program need rather than org chart



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At SPECTRAFORCE, we are committed to maintaining a workplace that ensures fair compensation and wage transparency in adherence with all applicable state and local laws. This position's starting pay is: $55/hr.
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