QG
Physical Design Manager ( Fusion Compiler )
Accepting applicationsQuest Global · Sunnyvale, CA
Full-Time Mid_senior CalibreGenusInnovusMentorPerl
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Title :: Physical Design Technical Manager ( Fusion Compiler )
Location :: Santa Clara, CA
Work Experience
What You will Do
Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure
Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes
Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown
Develop and maintain automation flows using Tcl, Python, and Shell
Collaborate with cross-functional teams for design closure and signoff
Mentor and lead junior team members
Innovate and contribute to flow/methodology improvements
What You Will Bring:
Experience in physical design and timing closure
Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Fusion Compiler, Redhawk/Voltus, or Calibre
Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
Knowledge of geometry/process/device technology implications on physical design
10+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendors
Programming/scripting skills: TCL, Python, Perl or Shell
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Location :: Santa Clara, CA
Work Experience
What You will Do
Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure
Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes
Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown
Develop and maintain automation flows using Tcl, Python, and Shell
Collaborate with cross-functional teams for design closure and signoff
Mentor and lead junior team members
Innovate and contribute to flow/methodology improvements
What You Will Bring:
Experience in physical design and timing closure
Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Fusion Compiler, Redhawk/Voltus, or Calibre
Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
Knowledge of geometry/process/device technology implications on physical design
10+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendors
Programming/scripting skills: TCL, Python, Perl or Shell
Show more Show less