SS
Physical Design Manager
Accepting applicationsSmartSoC Solutions Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior CadenceCalibreDFTInnovusMentor
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Ideal Candidate:
An engineer with 8–12 years of experience who has led complex SoC physical design projects, worked on advanced technology nodes, contributed to methodology development, and demonstrated strong technical leadership and mentoring skills.
This role is for a senior Physical Design engineer with expertise in full-chip implementation at advanced technology nodes (7nm/5nm/3nm) and exposure to advanced packaging technologies such as Chiplets, 2.5D/3D IC, or HBM.
Key Responsibilities:
Lead end-to-end full-chip physical design from floorplanning to signoff.
Define and improve physical design methodologies, automation, and implementation flows.
Evaluate and adopt new process technologies and design techniques.
Collaborate with RTL, DFT, Packaging, Foundry, and STA teams to resolve design challenges.
Mentor junior engineers and provide technical leadership.
Drive timing, power, area, congestion, and signoff closure while resolving critical technical issues.
Establish design quality metrics and continuously improve implementation efficiency.
Required Skills:
Full-Chip Physical Design
Floorplanning, Placement, CTS, Routing, Timing Closure
Physical Verification (DRC/LVS), IR Drop, EM, SI
Advanced nodes (7nm or below)
Advanced Packaging (Chiplets, 2.5D/3D IC, HBM)
EDA Tools: Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre
Scripting: Tcl/Python (preferred)
Show more Show less
An engineer with 8–12 years of experience who has led complex SoC physical design projects, worked on advanced technology nodes, contributed to methodology development, and demonstrated strong technical leadership and mentoring skills.
This role is for a senior Physical Design engineer with expertise in full-chip implementation at advanced technology nodes (7nm/5nm/3nm) and exposure to advanced packaging technologies such as Chiplets, 2.5D/3D IC, or HBM.
Key Responsibilities:
Lead end-to-end full-chip physical design from floorplanning to signoff.
Define and improve physical design methodologies, automation, and implementation flows.
Evaluate and adopt new process technologies and design techniques.
Collaborate with RTL, DFT, Packaging, Foundry, and STA teams to resolve design challenges.
Mentor junior engineers and provide technical leadership.
Drive timing, power, area, congestion, and signoff closure while resolving critical technical issues.
Establish design quality metrics and continuously improve implementation efficiency.
Required Skills:
Full-Chip Physical Design
Floorplanning, Placement, CTS, Routing, Timing Closure
Physical Verification (DRC/LVS), IR Drop, EM, SI
Advanced nodes (7nm or below)
Advanced Packaging (Chiplets, 2.5D/3D IC, HBM)
EDA Tools: Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre
Scripting: Tcl/Python (preferred)
Show more Show less