Physical Design Manager

Company Description
Radiant Semiconductors is a VLSI services company specializing in Design Verification, DFT, Physical Design, Physical Verification, Analog Layout, and Analog Circuit Design for globally renowned clients. The company has expanded its expertise to include services in the Embedded, Automotive, and Software domains. With a focus on innovation and excellence, Radiant Semiconductors delivers advanced design solutions tailored to the industry's evolving needs.

Role Description
This is a full-time, on-site role based in Bengaluru South for a Physical Design Professional. Key responsibilities include analyzing and implementing design logic from RTL to GDSII stages, optimizing designs for performance, power, and area, resolving timing issues, delivering sign-off quality layouts, and collaborating with cross-functional teams to meet project milestones.

𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 10–20 Years
𝗡𝗼𝘁𝗶𝗰𝗲 𝗣𝗲𝗿𝗶𝗼𝗱: Immediate to 30 Days
𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: Bangalore

Key Responsibilities
Lead full-chip Place and Route (PnR) execution on advanced nodes (2nm, 3nm, 4nm) with full ownership of design quality and timelines
Drive full-chip design planning and strategy including floorplan architecture, hierarchical design methodology, and integration roadmaps
Own end-to-end full-chip integration coordinating block-level designs, power delivery, clock distribution, and cross-block signal integrity
Develop and implement PnR strategies including macro placement, block-level integration, power distribution networks (PDN), and clock tree synthesis (CTS)
Drive design optimization for power, performance, and area (PPA) with deep focus on power efficiency and thermal management across the full chip
Lead cross-functional collaboration with frontend design, block-level teams, verification, physical design, and manufacturing teams for seamless integration
Mentor and guide junior physical design engineers in best practices, tool workflows, full-chip methodology, and technical excellence
Own timing closure and signoff readiness at full-chip level, including static timing analysis, IR drop analysis, electromigration checks, and reliability assessment
Navigate advanced technology constraints including multi-patterning, design rules, lithography effects, and process design kit (PDK) optimization
Participate in design reviews and provide technical expertise on full-chip implementation trade-offs and integration challenges
Optimize tool flows and automation to improve full-chip design productivity and overall design quality
Ensure compliance with manufacturing requirements and design rules for yield optimization across the entire silicon

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