MT

Physical Design Manager

Accepting applications

Mirafra Technologies · Bengaluru, Karnataka, India

Full-Time Mid_senior FloorplanningP&RSTAIR/EMPhysical Verification
Estimated market salary
₹11-20 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
🚀 Greetings from #Mirafra Technologies! 🚀
💼 Position: Physical Design – SoC Full Chip Lead
🔹 Key Responsibilities:
✔ Own Physical Design for advanced technology nodes
✔ Drive full-chip floorplanning based on architecture
✔ Define timing targets across PVTs
✔ Lead full-chip & tile P&R closure
✔ Drive signoff activities including Physical Verification, IREM, and related flows
✔ Collaborate with Architects, IP, CAD/Methodology, Package, and cross-functional PD teams
✔ Optimize PPA, datapath latency, and power delivery
🎯 What We're Looking For:
✅ 15+ years of experience in SoC Physical Design with full-chip ownership and signoff
✅ Strong expertise in advanced-node implementation
✅ Excellent communication, stakeholder management, and presentation skills
✅ Ability to collaborate effectively with global teams and senior architects
🎓 Education: Bachelor's or Master's degree in a relevant engineering discipline.
📩 Interested or know someone who fits the role?
Please share your profile or refer suitable candidates at jyotijha@mirafra.com.
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