Physical Design Manager

Physical Design Manager
Location: Bengaluru
Experience: 10–15 Years
Role Overview:
We are seeking a highly skilled Physical Design Manager to lead end-to-end implementation and signoff of complex SoCs across advanced technology nodes. The role requires strong technical leadership with hands-on expertise in physical design methodologies, PPA optimization, and full-chip convergence.
Key Responsibilities
Drive complete physical design execution from floorplanning to tapeout.
Lead block/full-chip implementation including power planning, CTS, routing, timing closure, and ECO closure.
Own signoff activities covering STA, SI, IR drop, EM, and physical verification.
Drive PPA optimization and methodology improvements across advanced nodes.
Collaborate closely with RTL, STA, DFT, Packaging, and Foundry teams to ensure design convergence.
Develop and enhance automation flows using Tcl, Python, and Perl.
Mentor engineers and provide technical guidance for complex implementation challenges.
Technical Skills:
Strong expertise in Floorplanning, Power Planning, CTS, Place & Route, Timing Closure, and ECO implementation.
Hands-on experience with Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
Deep understanding of PrimeTime, StarRC, Calibre, RedHawk/Voltus, SI, IR/EM analysis, and physical verification flows.
Experience with advanced technology nodes (7nm/5nm/3nm and below) and hierarchical SoC designs.
Strong scripting skills in Tcl, Python, and Perl.
Exposure to low-power implementation, multi-voltage designs, and chip-package interactions is preferred.
Qualifications:
B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, or related disciplines.
Proven experience delivering multiple complex SoCs to silicon with strong technical ownership.
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