Physical Design Lead – Place & Route (PnR) / Static Timing Analysis (STA)

Physical Design Lead Place & Route (PnR) / Static Timing Analysis (STA)
Location: Bengaluru, India
Work Mode: Onsite
Experience: 8 -15 Years
Industry: Semiconductor / VLSI / ASIC Design

Role Overview

We are seeking an experienced Physical Design Lead to drive the complete physical implementation flow for complex ASIC and SoC designs targeting advanced semiconductor technologies. The role involves leading Place & Route (PnR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification, Power Optimization, and Signoff while collaborating closely with RTL, DFT, Design Verification, Package, and Product Engineering teams.
The ideal candidate will have extensive experience delivering multiple successful tape-outs across advanced process nodes and possess strong leadership capabilities to mentor engineering teams and drive high-quality silicon implementation.
Key Responsibilities
Lead complete ASIC/SoC physical design implementation from netlist through GDSII signoff.
Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification activities.
Perform timing closure across multiple process, voltage, and temperature (PVT) corners.
Optimize designs for Power, Performance, and Area (PPA) while meeting schedule and quality objectives.
Conduct Static Timing Analysis (STA) and resolve setup, hold, clock skew, and signal integrity issues.
Perform physical verification including DRC, LVS, ERC, antenna, and electromigration (EM/IR) analysis.
Collaborate with RTL, DFT, Design Verification, Package Design, and Process Technology teams throughout the design cycle.
Lead engineering reviews, design signoff, ECO implementation, and tape-out readiness activities.
Develop and enhance physical design methodologies, automation flows, and reusable scripts.
Mentor junior engineers and provide technical leadership across multiple projects.
Support silicon bring-up and post-silicon debug where required.
Coordinate with global engineering teams to ensure successful execution of complex semiconductor programs.
Required Qualifications
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
8 15 years of hands-on experience in ASIC or SoC Physical Design.
Proven experience leading successful tape-outs in advanced technology nodes.
Strong understanding of the complete semiconductor implementation flow.
Technical Skills Physical Design
Floorplanning
Power Planning
Placement
Clock Tree Synthesis (CTS)
Routing
Physical Optimization
ECO Implementation
GDSII Generation
Timing & Signoff
Static Timing Analysis (STA)
Timing Closure
Multi-Mode Multi-Corner (MMMC)
OCV / AOCV / POCV
Crosstalk Analysis
Signal Integrity
Clock Optimization
Physical Verification
Design Rule Check (DRC)
Layout Versus Schematic (LVS)
Electrical Rule Check (ERC)
Antenna Checks
EM/IR Analysis
IR Drop Analysis
Reliability Verification
EDA Tools
Cadence Innovus
Synopsys ICC2
PrimeTime
Tempus
StarRC
Calibre
Pegasus
RedHawk
Voltus
Programming & Automation
Tcl
Perl
Python
Shell Scripting


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