Physical Design Lead(High Speed IP's)

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

PMTS SILICON DESIGN ENGINEER

THE ROLE

AMD is looking for an experienced and highly motivated Principal Member of Technical Staff (PMTS) to join the CT Physical Design team. In this role, you will drive the physical implementation of industry-leading high-speed interface IPs including DDR, LPDDR, GDDR, PCIe, and other next-generation mixed-signal PHY solutions used across client, server, and graphics products.

As a technical leader, you will work closely with architects, circuit designers, RTL, package, power integrity, signal integrity, SoC, and methodology teams to define and implement innovative physical design solutions that achieve aggressive PPA, frequency, power, and schedule goals on advanced process nodes.

The ideal candidate combines deep physical design expertise with strong leadership capabilities and a proven track record of delivering complex, high-performance IPs to production.

THE PERSON

You are passionate about solving complex physical design challenges in advanced semiconductor technologies. You thrive in fast-paced environments, influence technical direction beyond your immediate team, and enjoy mentoring engineers while driving innovation in implementation methodologies.

You possess deep understanding of high-speed digital and mixed-signal design implementation and have successfully delivered multiple tape-outs in advanced technology nodes.

Key Responsibilities

Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, SerDes, and related subsystems.
Drive architecture and physical design co-optimization to achieve industry-leading Power, Performance, and Area (PPA).
Own end-to-end implementation activities including:
Floorplanning
Power planning
Placement
Clock architecture
CTS
Timing closure
Signal integrity closure
Physical verification
Tapeout signoff
Drive high-frequency timing closure for challenging datapaths and clock distribution networks.
Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency.
Develop and deploy innovative implementation methodologies to improve design quality, productivity, and scalability.
Collaborate with cross-functional teams including Architecture, RTL, AMS, Package, SI/PI, Product Engineering, SoC, CAD, and EDA vendors.
Debug and resolve complex implementation, silicon correlation, and post-silicon issues.
Provide technical leadership for multiple projects and influence implementation strategies across organizational boundaries.
Mentor SMTS/MTS engineers and help grow the technical capability of the organization.
Drive continuous improvement initiatives in automation, AI-assisted design methodologies, and signoff flows.

Preferred Experience

15+ years of industry experience in Physical Design for advanced semiconductor products.
Proven track record delivering multiple successful tape-outs on advanced technology nodes (N3/N4/N5 or equivalent).
Extensive experience with high-performance and high-speed interface IPs such as:
DDR4/DDR5/LPDDR5/LPDDR6
GDDR
PCIe
Mixed-signal PHYs
Deep expertise in:
Timing closure
Clock design
Physical implementation
Power optimization
Signal integrity
Multi-voltage design methodologies
Strong understanding of:
Package interactions
RDL
ESD considerations
Analog integration challenges
Power integrity
Experience closing timing at aggressive frequencies and implementing complex clocking structures.
Expertise with industry-standard EDA tools including Cadence and Synopsys implementation/signoff flows.
Experience driving methodology development and automation.
Demonstrated leadership across cross-functional teams and geographies.

Technical Skills

Physical Design and Signoff
STA and Timing Closure
Clock Architecture and CTS
Floorplanning and Power Planning
IR/EM Analysis
Physical Verification
SI/PI Analysis
Low Power Design (UPF/CPF)
Advanced Node Design Methodologies
Tcl/Python/Scripting
AI-assisted Design Flows (preferred)


LEADERSHIP EXPECTATIONS

Recognized technical expert in physical design and implementation.
Influences technical direction beyond immediate project boundaries.
Leads strategic technical initiatives across multiple IP programs.
Mentors and develops engineering talent.
Drives innovation that improves product competitiveness, engineering productivity, and design quality.


EDUCATION

BS/MS in Electrical Engineering, Computer Engineering, VLSI Design, or related field.
PhD preferred but not required.


Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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