Physical Design Lead

Physical Design Lead
Experience: 14+ Years
Function: VLSI / ASIC Physical Design
Level: Senior Leadership / Technical Lead
Location: Bengaluru/ Hyderabad

Job Description:
We are looking for an experienced Physical Design Lead with a minimum of 14+ years of expertise in ASIC/VLSI physical design and a strong full-chip implementation background. The role will be responsible for driving physical implementation, timing closure, power convergence, and sign-off of complex, high-frequency and low-power SoCs.
The ideal candidate should have strong hands-on experience across the complete RTL-to-GDSII flow, including synthesis, floor planning, physical synthesis, placement, CTS, routing, timing analysis, ECO implementation, and physical design closure. Experience working with ASIC vendors and cross-functional Systems, Architecture, Application and Design teams is essential.

Key Responsibilities
Lead full-chip physical design and implementation of complex ASIC/SoC designs from RTL to GDSII.
Drive timing closure through physical synthesis, Place & Route, timing optimization and ECO implementation.
Own and drive the complete front-end to back-end implementation flow, including:
RTL synthesis
Formal verification (FV)
Floorplanning
Netlisting
Placement and routing
Timing constraints
Timing analysis and optimization
Power convergence
ECO implementation
Physical and timing sign-off
Perform hands-on physical implementation and timing closure for core platforms and SoCs.
Drive physical design and timing convergence at block, cluster and full-chip levels.
Lead physical design closure for large and complex designs operating at 1 GHz+ frequencies.
Own Clock Tree Synthesis (CTS) and clock distribution for high-frequency designs.
Work closely with Systems and Application teams to develop timing-closure-friendly SoC architectures and IO interfaces.
Drive IO planning and IO pin optimization in alignment with overall chip architecture and timing requirements.
Define and streamline timing sign-off criteria, timing analysis methodologies and implementation flows.
Develop and enhance automation scripts for timing closure and automatic ECO generation.
Support critical-path analysis, including SPICE-based simulation and analysis where required.
Drive physical implementation and timing convergence for high-frequency, low-power CPU, GPU and/or ASIC designs.
Collaborate with ASIC vendors and internal design teams to resolve implementation challenges and achieve schedule, PPA and sign-off targets.
Identify physical design bottlenecks and drive optimization across performance, power and area (PPA).
Provide technical leadership and guidance on physical design methodologies, flows and best practices.

Required Skills & Experience
14+ years of relevant experience in ASIC/VLSI Physical Design.
Mandatory: Proven full-chip physical design experience.
Strong hands-on experience with the RTL-to-GDSII physical implementation flow.
Strong expertise in:
Physical synthesis
Floorplanning
Placement & Routing
Clock Tree Synthesis (CTS)
Timing analysis and closure
Timing constraints
ECO implementation
Power optimization and convergence
Physical design sign-off
Experience with 1 GHz+ high-frequency designs is highly desirable.
Strong experience in full-chip timing closure for complex SoCs.
Experience with CPU, GPU and/or complex ASIC/SoC designs, preferably in high-performance and low-power environments.
Strong understanding of clock distribution, CTS and clock optimization.
Experience working with ASIC vendors and external implementation teams.
Strong understanding of timing sign-off methodologies and timing analysis flows.
Experience developing or enhancing automation scripts for timing closure / ECO generation.
Exposure to critical-path SPICE simulation and analysis.
Strong understanding of PPA optimization and design trade-offs.
Ability to work closely with Architecture, Systems, RTL, Design, Verification and Application teams.

Preferred Technical Expertise
Experience with industry-standard Physical Design / Place & Route tools.
Strong understanding of advanced-node physical design challenges.
Experience with high-performance, low-power SoC implementation.
Experience handling complex timing scenarios and multi-corner/multi-mode timing closure.
Strong scripting/automation skills using Tcl, Python, Perl or similar languages.
*Full-chip experience is mandatory; candidates with only block-level physical design experience would not be suitable for this role.

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