IG
Physical Design Lead
Accepting applicationsInsight Global · North Reading, MA
Full-Time Mid_senior ASICCadencePCIePythonRTL
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Role Title: Physical Design Lead
Location: North Reading, MA (relocation offered)
Role Type: Permanent
Pay Rate: $200k - $250k base + bonuses, RSUs and benefits
Required Skills & Experience
10+ years of hands-on ASIC physical design experience, including leadership of large/complex PD projects
Experience at advanced technology nodes (16nm>)
Deep expertise in RTL-to-GDSII flows and timing closure
Strong understanding of STA, constraints development, and signoff methodologies
Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
Proficiency with EDA tools (Cadence preferred)
Strong scripting and automation skills using Tcl, Python, and/or equivalent
BS or MS in Electrical Engineering
Job Description
Insight Global is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to next-generation SoC and memory test platforms. In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.
Key Responsibilities:
Lead and mentor a team of physical design engineers across the full project lifecycle
Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
Develop and own chip floorplans, timing budgets, power estimates, and pin planning
Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
Support hands-on place-and-route (P&R) for critical and high-speed blocks
Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
Ensure robust signoff closure including DRC/LVS and EM/IR analysis
Develop, enhance, and maintain physical design tool flows and automation
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Location: North Reading, MA (relocation offered)
Role Type: Permanent
Pay Rate: $200k - $250k base + bonuses, RSUs and benefits
Required Skills & Experience
10+ years of hands-on ASIC physical design experience, including leadership of large/complex PD projects
Experience at advanced technology nodes (16nm>)
Deep expertise in RTL-to-GDSII flows and timing closure
Strong understanding of STA, constraints development, and signoff methodologies
Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
Proficiency with EDA tools (Cadence preferred)
Strong scripting and automation skills using Tcl, Python, and/or equivalent
BS or MS in Electrical Engineering
Job Description
Insight Global is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to next-generation SoC and memory test platforms. In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.
Key Responsibilities:
Lead and mentor a team of physical design engineers across the full project lifecycle
Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
Develop and own chip floorplans, timing budgets, power estimates, and pin planning
Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
Support hands-on place-and-route (P&R) for critical and high-speed blocks
Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
Ensure robust signoff closure including DRC/LVS and EM/IR analysis
Develop, enhance, and maintain physical design tool flows and automation
Show more Show less