E(
Physical Design Lead
Accepting applicationseInfochips (An Arrow Company) · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICDFTRTLmentor
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
India
Company Description eInfochips, an Arrow company, is a global provider of product engineering and semiconductor design services with over 500 products developed and more than 40 million deployments across 140 countries. The company drives innovation across digital transformation, connected IoT solutions, and cloud platforms such as AWS and Azure. Its portfolio spans silicon engineering (including physical design and DFT), embedded systems, software engineering, and extended services for product lifecycle management. eInfochips emphasizes a culture of innovation, collaboration, and professional growth, recognizing that its success depends on the skills and quality of its people. Candidates can explore more about the company’s work and culture through its online presence and corporate resources.
Role Description The Physical Design Lead is a full-time, on-site role based in Bengaluru, responsible for driving end-to-end physical design activities for complex ASIC projects. In this position, the individual leads floorplanning, place-and-route, clock tree synthesis, power planning, and timing closure, while ensuring adherence to performance, area, and power targets. The role involves collaborating closely with front-end design, verification, and DFT teams to resolve design issues and optimize implementation. The Physical Design Lead is expected to define and refine physical design methodologies, guide junior engineers, review their work, and ensure high-quality deliverables that meet project schedules. The role also includes participating in design reviews, supporting sign-off (timing, power, signal integrity, physical verification), and contributing to continuous improvement of internal frameworks and flows.
Qualifications
Strong expertise in ASIC physical design flows, including floorplanning, place-and-route, clock tree synthesis, power planning, and timing closure.
Hands-on experience with industry-standard EDA tools for physical design, timing analysis, physical verification, and power/IR-drop analysis.
Solid understanding of digital design fundamentals, RTL-to-GDSII flow, fabrication processes, and constraints related to performance, power, and area.
Experience collaborating with front-end design, verification, and DFT teams to debug and resolve implementation and timing issues.
Demonstrated ability to lead projects, mentor team members, review design work, and drive quality and schedule adherence.
Strong problem-solving skills, attention to detail, and the ability to document methodologies and contribute to reusable frameworks.
Effective communication and interpersonal skills to work with cross-functional and global teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
Prior experience in advanced technology nodes and complex, high-speed or low-power designs is highly beneficial.
Show more Show less
Role Description The Physical Design Lead is a full-time, on-site role based in Bengaluru, responsible for driving end-to-end physical design activities for complex ASIC projects. In this position, the individual leads floorplanning, place-and-route, clock tree synthesis, power planning, and timing closure, while ensuring adherence to performance, area, and power targets. The role involves collaborating closely with front-end design, verification, and DFT teams to resolve design issues and optimize implementation. The Physical Design Lead is expected to define and refine physical design methodologies, guide junior engineers, review their work, and ensure high-quality deliverables that meet project schedules. The role also includes participating in design reviews, supporting sign-off (timing, power, signal integrity, physical verification), and contributing to continuous improvement of internal frameworks and flows.
Qualifications
Strong expertise in ASIC physical design flows, including floorplanning, place-and-route, clock tree synthesis, power planning, and timing closure.
Hands-on experience with industry-standard EDA tools for physical design, timing analysis, physical verification, and power/IR-drop analysis.
Solid understanding of digital design fundamentals, RTL-to-GDSII flow, fabrication processes, and constraints related to performance, power, and area.
Experience collaborating with front-end design, verification, and DFT teams to debug and resolve implementation and timing issues.
Demonstrated ability to lead projects, mentor team members, review design work, and drive quality and schedule adherence.
Strong problem-solving skills, attention to detail, and the ability to document methodologies and contribute to reusable frameworks.
Effective communication and interpersonal skills to work with cross-functional and global teams.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
Prior experience in advanced technology nodes and complex, high-speed or low-power designs is highly beneficial.
Show more Show less