ST
PHYSICAL DESIGN LEAD (6+ years)
Accepting applicationsSiplont Technologies · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICCadenceDFTMentorPerl
Estimated market salary
₹20-36 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
20h ago
Category
Design
Experience
Mid_senior
Country
India
Company Description Siplont Technologies is a leading provider of semiconductor design and embedded technology solutions, helping businesses innovate faster and meet their product goals. The company delivers end-to-end design services that reduce time-to-market and support customers in staying competitive. Its team of experienced professionals and industry leaders brings deep expertise in semiconductor design, embedded systems, and advanced technologies. Siplont focuses on tailored, scalable solutions that ensure seamless integration and high performance for each client. Guided by a customer-centric and collaborative approach, the company is dedicated to designing next-generation semiconductors and optimizing embedded systems for success in a rapidly evolving technological landscape.
Role Description The Physical Design Lead is a full-time, on-site role based in Bengaluru. This role is responsible for leading and executing physical design activities for complex SoCs and ASICs, including floorplanning, place-and-route, clock tree synthesis, and timing closure. The Physical Design Lead will collaborate closely with RTL design, verification, and DFT teams to ensure clean handoff, robust implementation, and sign-off across PPA (power, performance, area) targets. Daily responsibilities include managing physical design flows, driving EDA tool optimization, reviewing layout quality, addressing congestion and IR drop issues, and ensuring compliance with design and manufacturing guidelines. The role also involves mentoring team members, coordinating project schedules and deliverables, and contributing to continuous improvement of methodologies and best practices.
Qualifications
Candidates should possess strong skills in physical design implementation, including floorplanning, placement, routing, and clock tree synthesis for SoC/ASIC designs.
Candidates should possess expertise in timing analysis and closure, power optimization, signal integrity, IR drop analysis, and design for manufacturability.
Candidates should possess proficiency with industry-standard EDA tools (such as Cadence, Synopsys, or Mentor) and scripting skills in languages like TCL, Python, or Perl for flow automation.
Candidates should possess experience collaborating with RTL, verification, and DFT teams, with the ability to review specifications and provide implementation feedback.
Candidates should possess strong problem-solving, analytical, and debugging skills, with attention to detail in design quality and sign-off criteria.
Candidates should possess leadership capabilities, including mentoring engineers, coordinating tasks, and communicating effectively with cross-functional stakeholders.
A bachelor’s or master’s degree in Electrical Engineering, Electronics, or a related discipline is preferred, along with prior experience in physical design lead or senior physical design roles.
Experience in advanced process nodes, multi-voltage and low-power design techniques, and familiarity with industry standards and best practices will be beneficial.
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Role Description The Physical Design Lead is a full-time, on-site role based in Bengaluru. This role is responsible for leading and executing physical design activities for complex SoCs and ASICs, including floorplanning, place-and-route, clock tree synthesis, and timing closure. The Physical Design Lead will collaborate closely with RTL design, verification, and DFT teams to ensure clean handoff, robust implementation, and sign-off across PPA (power, performance, area) targets. Daily responsibilities include managing physical design flows, driving EDA tool optimization, reviewing layout quality, addressing congestion and IR drop issues, and ensuring compliance with design and manufacturing guidelines. The role also involves mentoring team members, coordinating project schedules and deliverables, and contributing to continuous improvement of methodologies and best practices.
Qualifications
Candidates should possess strong skills in physical design implementation, including floorplanning, placement, routing, and clock tree synthesis for SoC/ASIC designs.
Candidates should possess expertise in timing analysis and closure, power optimization, signal integrity, IR drop analysis, and design for manufacturability.
Candidates should possess proficiency with industry-standard EDA tools (such as Cadence, Synopsys, or Mentor) and scripting skills in languages like TCL, Python, or Perl for flow automation.
Candidates should possess experience collaborating with RTL, verification, and DFT teams, with the ability to review specifications and provide implementation feedback.
Candidates should possess strong problem-solving, analytical, and debugging skills, with attention to detail in design quality and sign-off criteria.
Candidates should possess leadership capabilities, including mentoring engineers, coordinating tasks, and communicating effectively with cross-functional stakeholders.
A bachelor’s or master’s degree in Electrical Engineering, Electronics, or a related discipline is preferred, along with prior experience in physical design lead or senior physical design roles.
Experience in advanced process nodes, multi-voltage and low-power design techniques, and familiarity with industry standards and best practices will be beneficial.
Show more Show less
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