I
Physical Design Engineer - Synopsys DCnext
Accepting applicationsIBM · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICDFTRTLSoCSynopsys
Posted
29 May
Category
Design
Experience
Mid_senior
Country
India
Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Job Summary
Your role and responsibilities
We are seeking an experienced ASIC Synthesis Engineer with strong expertise in Synopsys Design Compiler NXT (DCnext) to drive high-quality RTL-to-Gates implementation. The candidate will be responsible for synthesis, optimization, and timing closure of complex SoC/ASIC designs in advanced technology nodes.
Key Responsibilities
Perform RTL synthesis using Synopsys Design Compiler NXT (DCnext)
Develop and maintain TCL-based synthesis scripts and flows
Drive timing closure and fix setup/hold violations
Optimize area, power, and performance across PVT corners
Collaborate with RTL designers for design improvements
Define and validate SDC constraints
Debug synthesis and QoR issues
Support low-power synthesis flows (UPF/CPF)
Collaborate with Physical Design, STA, and DFT teams
Perform ECO synthesis
Ensure lint, CDC awareness, and synthesis checks
Preferred Education
Bachelor's Degree
Required Technical And Professional Expertise
5-8 years of Physical design Eng Exp
Strong hands-on experience with DCnext
Expertise in timing analysis and SDC constraints
Proficient in TCL and Verilog/SystemVerilog
Deep understanding of ASIC design flow
Knowledge of MCMM flows and low-power techniques
Preferred Technical And Professional Experience
Strong knowledge and hands-on experience in physical design methodologies, including:
Logic synthesis
Placement
Clock Tree Synthesis (CTS)
Routing
Good understanding of physical verification and reliability checks, including:
LVS, DRC
Noise analysis
Power analysis
Electromigration (EM) / IR verification
Strong teamwork and collaboration mindset with:
Good problem-solving skills
Effective communication skills
Demonstrated leadership capabilities
Hands-on experience with industry tools:
Fusion Compiler
PrimeTime
Formality
Exposure to advanced technology nodes:
7nm / 5nm / 3nm
Working knowledge of:
UPF (Unified Power Format)
DFT (Design for Test)
Experience in:
Flow automation and scripting
Show more Show less
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Job Summary
Your role and responsibilities
We are seeking an experienced ASIC Synthesis Engineer with strong expertise in Synopsys Design Compiler NXT (DCnext) to drive high-quality RTL-to-Gates implementation. The candidate will be responsible for synthesis, optimization, and timing closure of complex SoC/ASIC designs in advanced technology nodes.
Key Responsibilities
Perform RTL synthesis using Synopsys Design Compiler NXT (DCnext)
Develop and maintain TCL-based synthesis scripts and flows
Drive timing closure and fix setup/hold violations
Optimize area, power, and performance across PVT corners
Collaborate with RTL designers for design improvements
Define and validate SDC constraints
Debug synthesis and QoR issues
Support low-power synthesis flows (UPF/CPF)
Collaborate with Physical Design, STA, and DFT teams
Perform ECO synthesis
Ensure lint, CDC awareness, and synthesis checks
Preferred Education
Bachelor's Degree
Required Technical And Professional Expertise
5-8 years of Physical design Eng Exp
Strong hands-on experience with DCnext
Expertise in timing analysis and SDC constraints
Proficient in TCL and Verilog/SystemVerilog
Deep understanding of ASIC design flow
Knowledge of MCMM flows and low-power techniques
Preferred Technical And Professional Experience
Strong knowledge and hands-on experience in physical design methodologies, including:
Logic synthesis
Placement
Clock Tree Synthesis (CTS)
Routing
Good understanding of physical verification and reliability checks, including:
LVS, DRC
Noise analysis
Power analysis
Electromigration (EM) / IR verification
Strong teamwork and collaboration mindset with:
Good problem-solving skills
Effective communication skills
Demonstrated leadership capabilities
Hands-on experience with industry tools:
Fusion Compiler
PrimeTime
Formality
Exposure to advanced technology nodes:
7nm / 5nm / 3nm
Working knowledge of:
UPF (Unified Power Format)
DFT (Design for Test)
Experience in:
Flow automation and scripting
Show more Show less