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Physical Design Engineer & STA Engineer - 5+ Years - Bangalore Location
Accepting applicationsleadIC Design Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Entry STAPhysical DesignTiming AnalysisPrimeTimeInnovus
Estimated market salary
₹12-20 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
1d ago
Category
Design
Experience
Entry
Country
India
Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner that offers end-to-end services spanning custom, memory and analog layout, mixed-signal circuit design, digital design and RTL, verification, physical design, STA, DFT, and IP characterization. With engineering teams across India and Canada, LeadIC delivers high-quality design services tailored to product-driven teams and scalable offshore development centers. LeadIC emphasizes strong engineering ownership, quality-driven execution, and flexible engagement models, building long-term technical partnerships that help customers achieve silicon success.
Role Description This is a full-time, on-site role based in Bengaluru for a Physical Design Engineer & STA Engineer with 5+ years of relevant experience. The role involves owning the physical design flow from synthesis to place-and-route, clock tree synthesis, optimization, and timing closure for complex ASIC and SoC designs. Responsibilities include performing static timing analysis, identifying and resolving timing violations, collaborating with RTL and logic design teams on constraints and design changes, and driving signoff for timing, power, and area. The engineer will also work closely with physical verification teams to ensure DRC/LVS clean layouts, support ECO implementation, contribute to methodology and flow improvements, and participate in reviews and documentation to maintain high-quality delivery.
Qualifications
Strong expertise in Physical Design, including synthesis, floorplanning, place-and-route, clock tree synthesis, and optimization.
Hands-on experience with Static Timing Analysis (STA) and related timing signoff activities, with solid understanding of timing constraints and closure techniques.
Proficiency in Physical Verification flows, including DRC, LVS, and basic understanding of reliability and manufacturability checks.
Sound knowledge of Logic Design and RTL Design concepts, enabling effective collaboration with front-end design teams on constraints and ECOs.
Good understanding of Circuit Design fundamentals, timing, power, and signal integrity impacts on physical implementation.
Experience with industry-standard EDA tools for PD and STA (e.g., Synopsys, Cadence, Siemens) and familiarity with advanced process nodes.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
Effective communication, collaborative mindset, and ability to take ownership in a fast-paced, product-focused environment.
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Role Description This is a full-time, on-site role based in Bengaluru for a Physical Design Engineer & STA Engineer with 5+ years of relevant experience. The role involves owning the physical design flow from synthesis to place-and-route, clock tree synthesis, optimization, and timing closure for complex ASIC and SoC designs. Responsibilities include performing static timing analysis, identifying and resolving timing violations, collaborating with RTL and logic design teams on constraints and design changes, and driving signoff for timing, power, and area. The engineer will also work closely with physical verification teams to ensure DRC/LVS clean layouts, support ECO implementation, contribute to methodology and flow improvements, and participate in reviews and documentation to maintain high-quality delivery.
Qualifications
Strong expertise in Physical Design, including synthesis, floorplanning, place-and-route, clock tree synthesis, and optimization.
Hands-on experience with Static Timing Analysis (STA) and related timing signoff activities, with solid understanding of timing constraints and closure techniques.
Proficiency in Physical Verification flows, including DRC, LVS, and basic understanding of reliability and manufacturability checks.
Sound knowledge of Logic Design and RTL Design concepts, enabling effective collaboration with front-end design teams on constraints and ECOs.
Good understanding of Circuit Design fundamentals, timing, power, and signal integrity impacts on physical implementation.
Experience with industry-standard EDA tools for PD and STA (e.g., Synopsys, Cadence, Siemens) and familiarity with advanced process nodes.
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline.
Effective communication, collaborative mindset, and ability to take ownership in a fast-paced, product-focused environment.
Show more Show less