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Physical Design Engineer- CPU/GPU
Accepting applicationsMediaTek · Bengaluru, Karnataka, India
Full-Time Mid_senior RTL2GDSPhysical DesignTiming ClosurePlace and Route
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description
CPU/GPU R2G Engineer Responsible for RTL to GDS design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).
Main Requirements and Qualifications
At least 4 years of experience in Physical Design and Signoff
Skills:
>> Synthesis::
PPA improvement through synthesis recipe exploration for better perf, power, and area.
>> Physical design ::
Floor Planning, Place & Route followed by Timing and Physical Closure
>> Signoff ::
PI : PG mesh spec selection, Bump/RDL planning, IR closure
PV : DRC, LVS, ANT, ERC closure
STA : Block level timing closure
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CPU/GPU R2G Engineer Responsible for RTL to GDS design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).
Main Requirements and Qualifications
At least 4 years of experience in Physical Design and Signoff
Skills:
>> Synthesis::
PPA improvement through synthesis recipe exploration for better perf, power, and area.
>> Physical design ::
Floor Planning, Place & Route followed by Timing and Physical Closure
>> Signoff ::
PI : PG mesh spec selection, Bump/RDL planning, IR closure
PV : DRC, LVS, ANT, ERC closure
STA : Block level timing closure
Show more Show less