TG
Physical Design Engineer
Accepting applicationsTalent Groups · Mountain View, CA
Contract Mid_senior CalibreInnovusSOCSynopsys
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs.
Key Responsibilities:
Own Netlist-to-GDSII for high-speed, low-power SOC
Floorplanning, Placement, CTS, Routing, Timing closure
Drive PPA optimization - Power, Performance, Area for 2nm/3nm
Handle advanced nodes issues: IR Drop, EM, Crosstalk etc
Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre
Very Imp Skill: Innovus, 2nm, 3nm, 4nm, 5nm
Experience:
5 -10 years in Physical Design
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Key Responsibilities:
Own Netlist-to-GDSII for high-speed, low-power SOC
Floorplanning, Placement, CTS, Routing, Timing closure
Drive PPA optimization - Power, Performance, Area for 2nm/3nm
Handle advanced nodes issues: IR Drop, EM, Crosstalk etc
Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre
Very Imp Skill: Innovus, 2nm, 3nm, 4nm, 5nm
Experience:
5 -10 years in Physical Design
Show more Show less