ST

Physical Design Engineer

Accepting applications

Saika Technologies Inc · San Francisco Bay Area

Full-Time Mid_senior CadenceInnovusPerlTCL
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Physical Design Engineer
Location: Bay Area, USA
Work Type: Must work from client office.
Physical Design (PD) Engineer.
Experience on the latest TSMC technology node N3 (recommended) and N4.
End to end PD experience with PnR, including EMIR & Physical verification (PV) hands on experience.
Setting up the PD flow from scratch and work towards signoff on the PD collaterals with strong debug knowledge.
Various flow includes
floor planning (both chip level and block level),
power grid design, power/signal integrity signoff, EM/IR signoff
place and route (PnR) , clock tree synthesis, timing closure,
physical verification (DRC/LVS/Antenna), DFM closure
Expertise in scripting skills in Unix shell scripting, TCL and Perl
Should Co-ordinate with different cross functional team.
Must have:
Cadence Innovus P&R tool experience which is Google primary tool.
N4 and below technology experience in end2end physical design and physical verification.
Strong scripting skill.

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