QG
Physical Design Engineer
Accepting applicationsQuest Global · Sunnyvale, CA
Full-Time Mid_senior ASICCadenceCalibreDFTInnovus
Posted
29 Apr
Category
Design
Experience
Mid_senior
Country
United States
Job Summary
We are looking for a skilled Physical Design Engineer with strong hands-on experience using Cadence Innovus for end-to-end physical design implementation. The ideal candidate will have solid exposure across the full PD flow, from netlist handoff to GDSII, and the ability to work independently on complex blocks or full-chip designs.
Key Responsibilities
Perform end-to-end Physical Design implementation using Cadence Innovus
Handle floorplanning, power planning, placement, CTS, routing, and signoff support
Optimize design for timing, power, and area (PPA)
Perform timing closure with setup/hold fixes across all modes and corners
Analyze and resolve physical and timing-related issues
Collaborate closely with STA, DFT, RTL, and signoff teams
Support ECO implementation and late-stage design changes
Ensure compliance with DRC, LVS, and antenna rules
Work with multiple technology nodes and process constraints
Required Skills & Qualifications
4–10 years of experience in Physical Design (4–8 years preferred)
Strong hands-on experience with Cadence Innovus
Good understanding of ASIC Physical Design flow
Experience in:
Floorplanning & power grid design
Placement and congestion optimization
Clock Tree Synthesis (CTS)
Routing and post-route optimization
Solid fundamentals in STA concepts
Familiarity with low-power design techniques
Proficient in Linux/Unix environment
Scripting knowledge in Tcl (Python/Perl is a plus)
Preferred / Good-to-Have Skills
Experience with advanced technology nodes (7nm and below is a plus)
Exposure to multi-voltage designs
Knowledge of signoff tools (PrimeTime, Calibre, etc.)
Experience working on large SoCs or complex blocks
Ability to mentor junior engineers (for senior candidates)
Soft Skills
Strong problem-solving and debugging skills
Good communication and cross-team collaboration ability
Ability to work independently with minimal supervision
Strong ownership mindset and attention to detail
Show more Show less
We are looking for a skilled Physical Design Engineer with strong hands-on experience using Cadence Innovus for end-to-end physical design implementation. The ideal candidate will have solid exposure across the full PD flow, from netlist handoff to GDSII, and the ability to work independently on complex blocks or full-chip designs.
Key Responsibilities
Perform end-to-end Physical Design implementation using Cadence Innovus
Handle floorplanning, power planning, placement, CTS, routing, and signoff support
Optimize design for timing, power, and area (PPA)
Perform timing closure with setup/hold fixes across all modes and corners
Analyze and resolve physical and timing-related issues
Collaborate closely with STA, DFT, RTL, and signoff teams
Support ECO implementation and late-stage design changes
Ensure compliance with DRC, LVS, and antenna rules
Work with multiple technology nodes and process constraints
Required Skills & Qualifications
4–10 years of experience in Physical Design (4–8 years preferred)
Strong hands-on experience with Cadence Innovus
Good understanding of ASIC Physical Design flow
Experience in:
Floorplanning & power grid design
Placement and congestion optimization
Clock Tree Synthesis (CTS)
Routing and post-route optimization
Solid fundamentals in STA concepts
Familiarity with low-power design techniques
Proficient in Linux/Unix environment
Scripting knowledge in Tcl (Python/Perl is a plus)
Preferred / Good-to-Have Skills
Experience with advanced technology nodes (7nm and below is a plus)
Exposure to multi-voltage designs
Knowledge of signoff tools (PrimeTime, Calibre, etc.)
Experience working on large SoCs or complex blocks
Ability to mentor junior engineers (for senior candidates)
Soft Skills
Strong problem-solving and debugging skills
Good communication and cross-team collaboration ability
Ability to work independently with minimal supervision
Strong ownership mindset and attention to detail
Show more Show less