PT
Physical Design Engineer
Accepting applicationsPQAngels Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior FloorplanningPlacementCTSRoutePhysical Verification
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
Company Description :
PQAngels Technologies is a specialized in building high-performance engineering teams for the Post Quantum era of innovation. The company connects cutting-edge technology organizations with highly skilled professionals in Semiconductors, Cloud Computing, and Data Storage ecosystems. PQAngels Technologies focuses on niche engineering roles, enabling clients to innovate faster while offering candidates access to advanced projects and career growth. Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions.
Role Summary : We are looking for experienced ASIC Physical Design Engineers responsible for end-to-end implementation from Netlist to GDSII. The ideal candidate must have expertise in timing closure, low power implementation and advanced node designs.
Direct Apply : https://pqangelstech.com/ Or Mail: Careers@pqangelstech.com
Requirements
Responsibilities :
Placement, CTS and routing.
Timing closure and ECO implementation.
PPA optimization.
IR Drop and EM analysis.
DRC/LVS/Antenna fixes.
Collaborate with RTL, DFT, STA and Verification teams.
Support tapeout activities.
Debug physical design issues independently.
Drive project deliverables and timelines
Required Technical Skills :
Cadence Innovus
Synopsys ICC2
PrimeTime
Tempus
RedHawk
Calibre
SoC, PCIe, DDR
TCL, Shell, Perl or Python scripting
Floorplanning and power planning.
Technology Nodes : 28nm, 16nm, 12nm, 7nm, 5nm and exposure to 3nm (good to have).
Qualifications : Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics or related field with 4–11 years of relevant experience.
Benefits
Benefits
Competitive compensation
Learning & career growth
Exposure to global semiconductor projects
Collaborative work environment
Opportunities to work on cutting-edge technologies
Continuous technical learning
Show more Show less
PQAngels Technologies is a specialized in building high-performance engineering teams for the Post Quantum era of innovation. The company connects cutting-edge technology organizations with highly skilled professionals in Semiconductors, Cloud Computing, and Data Storage ecosystems. PQAngels Technologies focuses on niche engineering roles, enabling clients to innovate faster while offering candidates access to advanced projects and career growth. Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions.
Role Summary : We are looking for experienced ASIC Physical Design Engineers responsible for end-to-end implementation from Netlist to GDSII. The ideal candidate must have expertise in timing closure, low power implementation and advanced node designs.
Direct Apply : https://pqangelstech.com/ Or Mail: Careers@pqangelstech.com
Requirements
Responsibilities :
Placement, CTS and routing.
Timing closure and ECO implementation.
PPA optimization.
IR Drop and EM analysis.
DRC/LVS/Antenna fixes.
Collaborate with RTL, DFT, STA and Verification teams.
Support tapeout activities.
Debug physical design issues independently.
Drive project deliverables and timelines
Required Technical Skills :
Cadence Innovus
Synopsys ICC2
PrimeTime
Tempus
RedHawk
Calibre
SoC, PCIe, DDR
TCL, Shell, Perl or Python scripting
Floorplanning and power planning.
Technology Nodes : 28nm, 16nm, 12nm, 7nm, 5nm and exposure to 3nm (good to have).
Qualifications : Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics or related field with 4–11 years of relevant experience.
Benefits
Benefits
Competitive compensation
Learning & career growth
Exposure to global semiconductor projects
Collaborative work environment
Opportunities to work on cutting-edge technologies
Continuous technical learning
Show more Show less