M
Physical Design Engineer
Accepting applicationsMaximaTek · Wyoming, United States
Full-Time Entry ASICCadenceCalibreInnovusMentor
Posted
1d ago
Category
Design
Experience
Entry
Country
United States
We are seeking a detail-oriented Physical Design Engineer to manage and oversee the daily operations of our ASIC/SoC design implementation and architecture workflows. In this role, you will act as the vital link between RTL design teams, foundry partners, and product engineering teams, ensuring that all physical implementation steps are conducted with maximum efficiency, cost-effectiveness, and adherence to strict industry standards and security regulations.
Core Responsibilities
Design & Implementation Management: Coordinate daily physical design activities, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and timing closure.
Regulatory Compliance: Maintain comprehensive design governance and documentation; ensure all intellectual property (IP) blocks and hardware security features align with international compliance laws, cybersecurity requirements, and company SOPs.
Data & Design Integrity: Perform accurate static timing analysis (STA), physical verification (DRC/LVS/ERC), and formal verification; ensure "ALCOA+" principles are applied to critical design databases, tape-out records, and simulation logs.
Risk Mitigation: Monitor design bottlenecks, electromigration (EM/IR) drop risks, and cross-talk violations; report significant layout disruptions or performance shortfalls promptly to management and stakeholders.
Quality Assurance: Author and maintain physical design specifications, constraints (SDC), and flow schemas; assist in internal and external audits to ensure GxP and ISO silicon integrity standards are met.
Vendor Liaison: Serve as the primary point of contact for external Electronic Design Automation (EDA) tool vendors, IP providers, and foundry representatives during performance reviews and technical audits.
Qualifications
Education: Bachelor’s degree in Electrical Engineering, Electronics & Communication Engineering, Computer Engineering, or a related quantitative field (Required).
Experience: 0–5 years of experience in RTL-to-GDSII implementation, physical verification, or hardware-heavy manufacturing environments.
Technical Skills (Required)
Strong understanding of semiconductor physics, digital electronics, and lean hardware management principles.
Proficiency in scripting languages (e.g., Tcl, Python, Perl) and modern physical design and verification suites (e.g., Synopsys Innovus/Primetime, Cadence, Siemens/Mentor Calibre).
Familiarity with advanced process nodes, timing closure methodologies, and version control systems (e.g., Git).
Excellent technical writing, design documentation, and organizational skills.
Preferred Skills
Certification (or specialized training) in advanced EDA tools and physical implementation methodologies.
Experience with medical device, automotive (ISO 26262), or pharmaceutical GxP-compliant hardware environments and safety-critical silicon systems.
Knowledge of power-intent management (UPF/CPF), signal integrity, and advanced packaging technologies.
What We Offer
Targeted Placement: Direct marketing to our network of hiring managers in the Manufacturing, Automotive, and MedTech industries.
Technical Resume Rebuild: Optimization of your profile to highlight silicon infrastructure expertise alongside physical design efficiency.
Interview Coaching: Guidance on behavioral interviews and technical physical design/STA case studies.
Ready to Take the Next Step?
Email your updated resume to: shrutika@maximatek.com
Show more Show less
Core Responsibilities
Design & Implementation Management: Coordinate daily physical design activities, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and timing closure.
Regulatory Compliance: Maintain comprehensive design governance and documentation; ensure all intellectual property (IP) blocks and hardware security features align with international compliance laws, cybersecurity requirements, and company SOPs.
Data & Design Integrity: Perform accurate static timing analysis (STA), physical verification (DRC/LVS/ERC), and formal verification; ensure "ALCOA+" principles are applied to critical design databases, tape-out records, and simulation logs.
Risk Mitigation: Monitor design bottlenecks, electromigration (EM/IR) drop risks, and cross-talk violations; report significant layout disruptions or performance shortfalls promptly to management and stakeholders.
Quality Assurance: Author and maintain physical design specifications, constraints (SDC), and flow schemas; assist in internal and external audits to ensure GxP and ISO silicon integrity standards are met.
Vendor Liaison: Serve as the primary point of contact for external Electronic Design Automation (EDA) tool vendors, IP providers, and foundry representatives during performance reviews and technical audits.
Qualifications
Education: Bachelor’s degree in Electrical Engineering, Electronics & Communication Engineering, Computer Engineering, or a related quantitative field (Required).
Experience: 0–5 years of experience in RTL-to-GDSII implementation, physical verification, or hardware-heavy manufacturing environments.
Technical Skills (Required)
Strong understanding of semiconductor physics, digital electronics, and lean hardware management principles.
Proficiency in scripting languages (e.g., Tcl, Python, Perl) and modern physical design and verification suites (e.g., Synopsys Innovus/Primetime, Cadence, Siemens/Mentor Calibre).
Familiarity with advanced process nodes, timing closure methodologies, and version control systems (e.g., Git).
Excellent technical writing, design documentation, and organizational skills.
Preferred Skills
Certification (or specialized training) in advanced EDA tools and physical implementation methodologies.
Experience with medical device, automotive (ISO 26262), or pharmaceutical GxP-compliant hardware environments and safety-critical silicon systems.
Knowledge of power-intent management (UPF/CPF), signal integrity, and advanced packaging technologies.
What We Offer
Targeted Placement: Direct marketing to our network of hiring managers in the Manufacturing, Automotive, and MedTech industries.
Technical Resume Rebuild: Optimization of your profile to highlight silicon infrastructure expertise alongside physical design efficiency.
Interview Coaching: Guidance on behavioral interviews and technical physical design/STA case studies.
Ready to Take the Next Step?
Email your updated resume to: shrutika@maximatek.com
Show more Show less