Physical Design Engineer

Key Responsibilities:
Perform synthesis using Cadence Genus for large, timing-challenged designs
Drive PPA (power, performance, area) optimization through synthesis and early implementation stages
Develop and refine floorplans using Cadence Innovus
Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs
Partner with external P&R teams to iterate toward timing closure and PPA optimization
Identify and address timing bottlenecks early in the flow to improve convergence
Preferred Qualifications:
Proven experience with large-scale SoC or AI-class designs
At least 5 years of PD experience
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams
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