LT
Physical Design Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICCalibreInnovusPerlPython
Posted
10 Jun
Category
Design
Experience
Mid_senior
Country
India
🚀 Hiring: Physical Design Engineer (3+ Years Experience) 🚀
We are looking for talented Physical Design Engineers to join our growing VLSI team!
📍 Location: Bangalore
💼 Experience: 3+ Years
🕒 Notice Period: Immediate to 30 Days Preferred
🔹 Key Responsibilities:
• Block-level Physical Design implementation from Floorplan to Signoff
• Floorplanning, Placement, CTS, Routing, and Physical Verification
• Timing Closure, DRV/DRC/LVS/ERC fixes
• Power Planning and IR Drop Analysis
• PPA Optimization and Congestion Management
• Collaboration with STA, RTL, and Verification teams for successful tapeouts
🔹 Required Skills:
• Strong expertise in Physical Design flow
• Experience in advanced technology nodes (28nm/16nm/7nm/5nm/3nm preferred)
• Hands-on experience with Fusion Compiler, ICC2, Innovus, PrimeTime, and Calibre
• Good understanding of STA, CTS, Signal Integrity, and Physical Verification
• Scripting knowledge in TCL/Perl/Python is an added advantage
🎓 Education:
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), VLSI Design, Microelectronics, or a related field.
Strong academic background in VLSI, Digital Electronics, Semiconductor Devices, and ASIC Design preferred.
Show more Show less
We are looking for talented Physical Design Engineers to join our growing VLSI team!
📍 Location: Bangalore
💼 Experience: 3+ Years
🕒 Notice Period: Immediate to 30 Days Preferred
🔹 Key Responsibilities:
• Block-level Physical Design implementation from Floorplan to Signoff
• Floorplanning, Placement, CTS, Routing, and Physical Verification
• Timing Closure, DRV/DRC/LVS/ERC fixes
• Power Planning and IR Drop Analysis
• PPA Optimization and Congestion Management
• Collaboration with STA, RTL, and Verification teams for successful tapeouts
🔹 Required Skills:
• Strong expertise in Physical Design flow
• Experience in advanced technology nodes (28nm/16nm/7nm/5nm/3nm preferred)
• Hands-on experience with Fusion Compiler, ICC2, Innovus, PrimeTime, and Calibre
• Good understanding of STA, CTS, Signal Integrity, and Physical Verification
• Scripting knowledge in TCL/Perl/Python is an added advantage
🎓 Education:
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), VLSI Design, Microelectronics, or a related field.
Strong academic background in VLSI, Digital Electronics, Semiconductor Devices, and ASIC Design preferred.
Show more Show less
Similar Jobs
M
PRINCIPAL RTL DESIGN
Micron · Boise, United States, North America
M
Principal Engineer, High‑Speed RTL Design
Micron · Bangalore, India, Asia
N
ASIC TOP Floorplan Design Engineer
NVIDIA · Shanghai, China, Asia
N
Senior System Software Engineer, SoC Power and Performance - O-RAN Infrastructure
NVIDIA · 3 Locations