LT
Physical Design Engineer
Accepting applicationsLeadSoc Technologies Pvt Ltd · Noida, Uttar Pradesh, India
Full-Time Mid_senior Place & RouteSTATiming ClosureSynthesisInnovus
Posted
19h ago
Category
Design
Experience
Mid_senior
Country
India
Job Description – Physical Design Engineer
Position: Physical Design Engineer
Location: Noida
Experience: 4–10 Years
Notice Period: Immediate Joiners Preferred
Job Summary
We are seeking an experienced Physical Design Engineer to work on cutting-edge ASIC/SoC designs. The ideal candidate should have hands-on experience across the complete physical design flow, strong timing closure expertise, and the ability to deliver high-quality designs within aggressive project timelines.
Key Responsibilities
Execute the complete Physical Design flow from Netlist to GDSII.
Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
Drive timing closure by resolving setup and hold violations.
Perform congestion analysis and optimize PPA (Power, Performance, Area).
Analyze and fix DRC, LVS, antenna, ERC, IR drop, and electromigration (EM) issues.
Implement ECOs for timing and functional changes.
Perform static timing analysis (STA) and signoff using industry-standard methodologies.
Work closely with RTL, DFT, Verification, and Signoff teams to achieve successful tape-outs.
Debug and resolve implementation issues while ensuring design quality and schedule adherence.
Support multiple projects across advanced technology nodes.
Required Skills
4–10 years of hands-on experience in ASIC Physical Design.
Strong expertise in the complete Physical Design flow.
Experience in Floorplanning, Placement, CTS, Routing, Timing Closure, Physical Verification, and ECO implementation.
Good understanding of STA concepts, clock tree optimization, and power optimization.
Experience with IR Drop, EM analysis, DRC/LVS closure, and signoff methodologies.
Hands-on experience with Synopsys ICC2/Fusion Compiler or Cadence Innovus.
Working knowledge of PrimeTime, StarRC, RedHawk/Voltus, Calibre, or equivalent signoff tools.
Experience with advanced technology nodes (16nm/7nm/5nm/3nm) is highly preferred.
Good scripting knowledge in Tcl, Shell, or Python is an added advantage.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.
Excellent analytical and debugging skills.
Strong communication and collaboration skills.
Experience in successful tape-outs is preferred.
Location: Noida
Experience: 4–10 Years
Joining: Immediate to 20 Days preferred
Show more Show less
Position: Physical Design Engineer
Location: Noida
Experience: 4–10 Years
Notice Period: Immediate Joiners Preferred
Job Summary
We are seeking an experienced Physical Design Engineer to work on cutting-edge ASIC/SoC designs. The ideal candidate should have hands-on experience across the complete physical design flow, strong timing closure expertise, and the ability to deliver high-quality designs within aggressive project timelines.
Key Responsibilities
Execute the complete Physical Design flow from Netlist to GDSII.
Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
Drive timing closure by resolving setup and hold violations.
Perform congestion analysis and optimize PPA (Power, Performance, Area).
Analyze and fix DRC, LVS, antenna, ERC, IR drop, and electromigration (EM) issues.
Implement ECOs for timing and functional changes.
Perform static timing analysis (STA) and signoff using industry-standard methodologies.
Work closely with RTL, DFT, Verification, and Signoff teams to achieve successful tape-outs.
Debug and resolve implementation issues while ensuring design quality and schedule adherence.
Support multiple projects across advanced technology nodes.
Required Skills
4–10 years of hands-on experience in ASIC Physical Design.
Strong expertise in the complete Physical Design flow.
Experience in Floorplanning, Placement, CTS, Routing, Timing Closure, Physical Verification, and ECO implementation.
Good understanding of STA concepts, clock tree optimization, and power optimization.
Experience with IR Drop, EM analysis, DRC/LVS closure, and signoff methodologies.
Hands-on experience with Synopsys ICC2/Fusion Compiler or Cadence Innovus.
Working knowledge of PrimeTime, StarRC, RedHawk/Voltus, Calibre, or equivalent signoff tools.
Experience with advanced technology nodes (16nm/7nm/5nm/3nm) is highly preferred.
Good scripting knowledge in Tcl, Shell, or Python is an added advantage.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field.
Excellent analytical and debugging skills.
Strong communication and collaboration skills.
Experience in successful tape-outs is preferred.
Location: Noida
Experience: 4–10 Years
Joining: Immediate to 20 Days preferred
Show more Show less