LI
Physical Design Engineer
Accepting applicationsLanceSoft, Inc. · San Jose, CA
Full-Time Mid_senior AIAnalogCadenceCalibreInnovus
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title - Physical Design Engineer
Job Location- San Jose-CA
Experienced Required - 12+ Years
Job Type - Full Time with Benefits
Job Description -
Requirement:
BS (Electrical)+ 12 years or MS (Electrical) +10 years of experience
Multiple tapeouts experience and extensive hands-on knowledge in various tools such as Innovus, VCLP, Formality, LEC, timing closure, and Calibre.
Cadence Innovus usage is essential.
TCL scripting is required, and Python is a plus
Job Description
Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm.
Physical implementation of the blocks and top-level.
Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation
Interfacing with internal and external teams, including Design, IPs, and Library
Physical Verification for block and chip-level
Static and Dynamic IR drop Analysis. Signal and Power EM checks
Methodology & Flow development of Physical Design & Timing Closure
Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent requirements
Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip-chip, wlcsp is a plus.
Knowledge of AI tools preferable.
1. Must have:
- block place & route extensive experience with Innovus or ICC2
- low-power implementation (multi-domain, retention, power-gating)
- timing closure hands-on (from custom clock tree to timing closure)
- physical verification
2. Huge plus for following knowledge as well:
- lead project
- chip-level integration
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Job Location- San Jose-CA
Experienced Required - 12+ Years
Job Type - Full Time with Benefits
Job Description -
Requirement:
BS (Electrical)+ 12 years or MS (Electrical) +10 years of experience
Multiple tapeouts experience and extensive hands-on knowledge in various tools such as Innovus, VCLP, Formality, LEC, timing closure, and Calibre.
Cadence Innovus usage is essential.
TCL scripting is required, and Python is a plus
Job Description
Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm.
Physical implementation of the blocks and top-level.
Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation
Interfacing with internal and external teams, including Design, IPs, and Library
Physical Verification for block and chip-level
Static and Dynamic IR drop Analysis. Signal and Power EM checks
Methodology & Flow development of Physical Design & Timing Closure
Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent requirements
Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip-chip, wlcsp is a plus.
Knowledge of AI tools preferable.
1. Must have:
- block place & route extensive experience with Innovus or ICC2
- low-power implementation (multi-domain, retention, power-gating)
- timing closure hands-on (from custom clock tree to timing closure)
- physical verification
2. Huge plus for following knowledge as well:
- lead project
- chip-level integration
Show more Show less