JV
Physical Design Engineer
Accepting applicationsJobs via Dice · San Jose, CA
Full-Time Senior CadenceCalibreDFTInnovusPerl
Posted
6d ago
Category
Design
Experience
Senior
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, Modern Agile Technologies, LLC, is seeking the following. Apply via Dice today!
Hiring !!!
Greerrtings from Modern Agile Technologies.
Position: Physical Design Engineer
Location: San Jose, CA (Onsite)
Type: Full Time
Experience: 6-15 years
Important pointers: profiles with most recent experience in Latest technology with Full PnR and Signoff Experience are desirable”. We also have feedback to look for folks (6 – 15 years exp) who can work in the high pressure environment.
What You will Do:
Perform physical design of 2nm/3nm mutli-GHz IP for network switch products. Be able to come up with floorplan, powerplan, cts and routing of the design using state-of-art EDA tools like Innovus. Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required.
What You Will Bring:
MSEE/MSCS 6+ years
Expertise in Cadence InnovAtop physical design tools
Experience on Calibre LVS/DRC
Low power, signal integrity experience
Work closely with RTL & DFT designers
Strong TCL/Python scripting knowledge required, Perl is a plus.
Show more Show less
Hiring !!!
Greerrtings from Modern Agile Technologies.
Position: Physical Design Engineer
Location: San Jose, CA (Onsite)
Type: Full Time
Experience: 6-15 years
Important pointers: profiles with most recent experience in Latest technology with Full PnR and Signoff Experience are desirable”. We also have feedback to look for folks (6 – 15 years exp) who can work in the high pressure environment.
What You will Do:
Perform physical design of 2nm/3nm mutli-GHz IP for network switch products. Be able to come up with floorplan, powerplan, cts and routing of the design using state-of-art EDA tools like Innovus. Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required.
What You Will Bring:
MSEE/MSCS 6+ years
Expertise in Cadence InnovAtop physical design tools
Experience on Calibre LVS/DRC
Low power, signal integrity experience
Work closely with RTL & DFT designers
Strong TCL/Python scripting knowledge required, Perl is a plus.
Show more Show less
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