IP
Physical Design Engineer
Accepting applicationsIntegrated Personnel Services Limited · Austin, TX
Full-Time Mid_senior ASICFinFETPerlPythonTcl
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Role: Physical Design Engineer
Location: Austin, TX and San Jose, CA (onsite)
Position: Full-Time
Experience Needed: 11+ years
H1B Transfer for this position are accepted
Relocation candidates are also accepted
This position is open for Austin, TX and San Jose, CA
Job Details:
Skills And Qualifications
11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
7+ years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
Strong experience with POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, Tempus), clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Strong knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
Strong analytical skills, attention to detail, and problem-solving skills using a data-driven approach.
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.
Nice to have:
Familiarity with advanced FinFET process nodes (5nm or smaller).
Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
Sign-off experience with reliability, signal integrity, noise, timing, and power
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Location: Austin, TX and San Jose, CA (onsite)
Position: Full-Time
Experience Needed: 11+ years
H1B Transfer for this position are accepted
Relocation candidates are also accepted
This position is open for Austin, TX and San Jose, CA
Job Details:
Skills And Qualifications
11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
7+ years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
Strong experience with POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g. PrimeTime, Tempus), clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Strong knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
Strong analytical skills, attention to detail, and problem-solving skills using a data-driven approach.
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.
Nice to have:
Familiarity with advanced FinFET process nodes (5nm or smaller).
Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
Sign-off experience with reliability, signal integrity, noise, timing, and power
Show more Show less