IG
Physical Design Engineer
Accepting applicationsInsight Global · United States
Full-Time Mid_senior ASICCMOSDFTJTAGPython
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Overview
We are seeking a Physical Design Engineer to support the implementation of complex ASIC/SoC designs from synthesis through tapeout. This role is responsible for physical design execution, timing closure, physical verification, DFT integration, and design optimization while collaborating with cross-functional engineering teams to deliver high-quality, manufacturable silicon.
Key Responsibilities
Perform full-chip and block-level physical design including synthesis, DFT integration, floorplanning, power planning, placement, CTS, routing, post-route optimization, and timing closure.
Drive timing closure across all corners and modes, addressing setup/hold, signal integrity, and IR/EM requirements.
Develop and improve physical design and DFT methodologies, flows, and automation.
Analyze and resolve timing, congestion, power, and implementation issues.
Perform physical verification including DRC, LVS, and antenna checks.
Support tapeout activities and assist with post-silicon debugging as needed.
Evaluate and integrate third-party IP, libraries, and design tools.
Automate repetitive design tasks using Python, Tcl, and shell scripting.
Collaborate with RTL, verification, and other engineering teams to ensure successful design integration.
Required Experience
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
3+ years of ASIC physical design experience with full-chip and/or large-block implementation.
Proven experience with synthesis, physical implementation, timing closure, DFT integration (scan, JTAG, MBIST, LBIST), and silicon tapeouts.
Strong knowledge of CMOS process technology, static timing analysis, timing constraints, power integrity, signal integrity, and DRC/LVS debugging.
Hands-on experience with Synopsys Design Compiler, ICC2/Fusion Compiler, PrimeTime, and StarRC.
Proficiency in scripting and automation using Python, Tcl, and shell.
Strong debugging, problem-solving, and collaboration skills.
Preferred Experience
Experience developing and improving physical design and DFT methodologies.
Experience integrating third-party IP, libraries, and EDA tools.
Experience supporting post-silicon validation and debugging.
Strong communication skills and ability to manage multiple priorities in a team-oriented environment.
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We are seeking a Physical Design Engineer to support the implementation of complex ASIC/SoC designs from synthesis through tapeout. This role is responsible for physical design execution, timing closure, physical verification, DFT integration, and design optimization while collaborating with cross-functional engineering teams to deliver high-quality, manufacturable silicon.
Key Responsibilities
Perform full-chip and block-level physical design including synthesis, DFT integration, floorplanning, power planning, placement, CTS, routing, post-route optimization, and timing closure.
Drive timing closure across all corners and modes, addressing setup/hold, signal integrity, and IR/EM requirements.
Develop and improve physical design and DFT methodologies, flows, and automation.
Analyze and resolve timing, congestion, power, and implementation issues.
Perform physical verification including DRC, LVS, and antenna checks.
Support tapeout activities and assist with post-silicon debugging as needed.
Evaluate and integrate third-party IP, libraries, and design tools.
Automate repetitive design tasks using Python, Tcl, and shell scripting.
Collaborate with RTL, verification, and other engineering teams to ensure successful design integration.
Required Experience
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
3+ years of ASIC physical design experience with full-chip and/or large-block implementation.
Proven experience with synthesis, physical implementation, timing closure, DFT integration (scan, JTAG, MBIST, LBIST), and silicon tapeouts.
Strong knowledge of CMOS process technology, static timing analysis, timing constraints, power integrity, signal integrity, and DRC/LVS debugging.
Hands-on experience with Synopsys Design Compiler, ICC2/Fusion Compiler, PrimeTime, and StarRC.
Proficiency in scripting and automation using Python, Tcl, and shell.
Strong debugging, problem-solving, and collaboration skills.
Preferred Experience
Experience developing and improving physical design and DFT methodologies.
Experience integrating third-party IP, libraries, and EDA tools.
Experience supporting post-silicon validation and debugging.
Strong communication skills and ability to manage multiple priorities in a team-oriented environment.
Show more Show less