Physical Design Engineer

Required Skills & Experience

- Bachelor's in electrical or computer engineering with 8+ years of experience, or Masters Degree with 6+ years
- 6+ years of experience in ASIC Physical Design with an emphasis on STA and timing
- Experience writing scripts in Python, TCL, and/or Bash
- Basic understanding of PLLs and clock networks - Familiar with design elements like flip flops, latches, memories, and logic gates
- Experience with STA tools like Synopsys Primetime, Cadence Tempus, Siemens Tessent
- Understanding of RC networks and how they affect the timing/propagation of signals
- Understanding of signal integrity, crosstalk delay, and glitch/noise analysis
- Understanding of setup analysis, hold analysis, and other timing checks
- Experience using SPICE analysis

Nice to Have Skills & Experience

- Experience with advanced STA concepts;
- POCV/SOCV/LVF modeling of variation
- MIS - multi-input switching
- CCS/ECSM/NLDM
- liberty timing models
- PBA - path based analysis
- LOCV/SOCV - location aware timing derates

Job Description

Insight Global is looking for a Senior level and Mid-Senior level STA Design Integration Engineers for a world class semiconductor ASIC provider that provides first time correct on schedule ASIC designs by relying on proven flows and methodology. As a STA DI Engineer you will join a highly skilled team of engineers that own the timing analysis and sign-off of complex ASICs. You will be responsible for the day-to-day timing closure and sign-off of complex ASIC designs, run and analyze static timing analysis (using tools like Synopsys Primetime or Cadence Tempus), debug timing violations such as setup/hold failures, and refine or create timing constraints to accurately model real chip behavior. You will investigate issues related to clock distribution (including PLLs and clock trees), signal integrity, and RC effects, while interpreting detailed timing reports and tool warnings to identify root causes. The role also involves writing scripts (Python, TCL, Bash) to automate flows, process large datasets, and improve efficiency, as well as leveraging knowledge of circuit elements like flip-flops, latches, memory, and CMOS logic to understand timing paths.

This is a direct hire position that also offers full benefits package, annual bonuses, substantial RSU packages, and full relocation provided.
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