C
Physical Design Engineer
Accepting applicationsCanvendor · California, United States
Contract Mid_senior AICadenceGenusInnovusRTL
Posted
1d ago
Category
Eda
Experience
Mid_senior
Country
United States
Job Title : Physical Design Engineer
Job Location : San Jose CA(Onsite)
Duration : 12+ Months
Job Description:
We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.
Key Responsibilities:
Perform synthesis using Cadence Genus for large, timing-challenged designs
Drive PPA (power, performance, area) optimization through synthesis and early implementation stages
Develop and refine floorplans using Cadence Innovus
Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs
Partner with external P&R teams to iterate toward timing closure and PPA optimization
Identify and address timing bottlenecks early in the flow to improve convergence
Preferred Qualifications:
Proven experience with large-scale SoC or AI-class designs
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams
Show more Show less
Job Location : San Jose CA(Onsite)
Duration : 12+ Months
Job Description:
We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.
Key Responsibilities:
Perform synthesis using Cadence Genus for large, timing-challenged designs
Drive PPA (power, performance, area) optimization through synthesis and early implementation stages
Develop and refine floorplans using Cadence Innovus
Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs
Partner with external P&R teams to iterate toward timing closure and PPA optimization
Identify and address timing bottlenecks early in the flow to improve convergence
Preferred Qualifications:
Proven experience with large-scale SoC or AI-class designs
Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
Strong understanding of timing closure and correlation between synthesis and implementation
Hands-on experience with Cadence Genus and Innovus
Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams
Show more Show less